Run Levinger

According to our database, Run Levinger authored at least 2 papers between 2018 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS.

Edwin Thaller, Run Levinger, Evgeny Shumaker, Aryeh Farber, Sergey Bershansky, Nir Geron, Ashoke Ravi, Rotem Banin, Jasmin Kadry, Gil Horovitz, Christian Krassnitzer, Christoph Duller, Patrick Torta, Mark Elzinga, Kamran Azadet

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2018

A Dual-Loop Synthesizer With Fast Frequency Modulation Ability for 77/79 GHz FMCW Automotive Radar Applications.

Jakob Vovnoboy, Run Levinger, Nadav Mazor, Danny Elad

IEEE J. Solid State Circuits, 2018