Ruili Ren

According to our database¹, Ruili Ren authored at least 3 papers in 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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PhD thesis

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Bibliography

2024

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique.

[BibT_eX]

[DOI]

Microelectron. J., 2024

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry.

[BibT_eX]

[DOI]

Microelectron. J., 2024

Ruili Ren

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