Rui Hou

Orcid: 0000-0002-9215-7632

Affiliations:
  • Institute of Information Engineering, Chinese Academy of Sciences, Beijing, China


According to our database1, Rui Hou authored at least 59 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
EnsGuard: A Novel Acceleration Framework for Adversarial Ensemble Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

A Hybrid Sparse-dense Defensive DNN Accelerator Architecture against Adversarial Example Attacks.
ACM Trans. Embed. Comput. Syst., September, 2024

Nacc-Guard: a lightweight DNN accelerator architecture for secure deep learning.
J. Supercomput., March, 2024

Elastic MSM: A Fast, Elastic and Modular Preprocessing Technique for Multi-Scalar Multiplication Algorithm on GPUs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Faster NTRU-based Bootstrapping in less than 4 ms.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

The Early Bird Catches the Leak: Unveiling Timing Side Channels in LLM Serving Systems.
CoRR, 2024

Taiyi: A high-performance CKKS accelerator for Practical Fully Homomorphic Encryption.
CoRR, 2024

NestedSGX: Bootstrapping Trust to Enclaves within Confidential VMs.
CoRR, 2024

SpecFL: An Efficient Speculative Federated Learning System for Tree-based Model Training.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
HE-Booster: An Efficient Polynomial Arithmetic Acceleration on GPUs for Fully Homomorphic Encryption.
IEEE Trans. Parallel Distributed Syst., April, 2023

Architecting the Autocuckoo Filter to Defend Against Cross-Core Cache Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

NTTFusion: Efficient Number Theoretic Transform Acceleration on GPUs.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

TensorFHE: Achieving Practical Computation on Encrypted Data Using GPGPU.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

ChaosINTC: A Secure Interrupt Management Mechanism against Interrupt-based Attacks on TEE.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Secure hybrid replacement policy: Mitigating conflict-based cache side channel attacks.
Microprocess. Microsystems, March, 2022

CPP: A lightweight memory page management extension to prevent code pointer leakage.
J. Syst. Archit., 2022

Remapped Cache Layout: Thwarting Cache-Based Side-Channel Attacks with a Hardware Defense.
CoRR, 2022

Defensive Design of Saturating Counters Based on Differential Privacy.
CoRR, 2022

Security Support on Memory Controller for Heap Memory Safety.
Proceedings of the IEEE International Conference on Trust, 2022

TACC: a secure accelerator enclave for AI workloads.
Proceedings of the SYSTOR '22: The 15th ACM International Systems and Storage Conference, Haifa, Israel, June 13, 2022

LAK: A Low-Overhead Lock-and-Key Based Schema for GPU Memory Safety.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

HyBP: Hybrid Isolation-Randomization Secure Branch Predictor.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

Conditional address propagation: an efficient defense mechanism against transient execution attacks.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Mimic Octopus Attack: Dynamic Camouflage Adversarial Examples Using Mimetic Feature for 3D Humans.
Proceedings of the Information Security and Cryptology - 18th International Conference, 2022

2021
Mitigating Cross-Core Cache Attacks via Suspicious Traffic Detection.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Exploiting Security Dependence for Conditional Speculation Against Spectre Attacks.
IEEE Trans. Computers, 2021

Line-Coalescing DRAM Cache.
Sustain. Comput. Informatics Syst., 2021

A Novel Probabilistic Saturating Counter Design for Secure Branch Predictor.
J. Comput. Sci. Technol., 2021

NASGuard: A Novel Accelerator Architecture for Robust Neural Architecture Search (NAS) Networks.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Punchcard: A Practical Red-Zone Based Scheme for Low-Overhead Heap Protection.
Proceedings of the 2021 IEEE 23rd Int Conf on High Performance Computing & Communications; 7th Int Conf on Data Science & Systems; 19th Int Conf on Smart City; 7th Int Conf on Dependability in Sensor, 2021

PiPoMonitor: Mitigating Cross-core Cache Attacks Using the Auto-Cuckoo Filter.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Lightweight Isolation Mechanism for Secure Branch Predictors.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

ShuffleFL: gradient-preserving federated learning using trusted execution environment.
Proceedings of the CF '21: Computing Frontiers Conference, 2021

2020
Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor.
IEEE Trans. Computers, 2020

Enabling Rack-scale Confidential Computing using Heterogeneous Trusted Execution Environment.
Proceedings of the 2020 IEEE Symposium on Security and Privacy, 2020

SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network Structure.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous Attacks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

RCecker: a lightweight rule-based mechanism for backward control-flow integrity.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

DNNGuard: An Elastic Heterogeneous DNN Accelerator Architecture against Adversarial Attacks.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
RAGuard: An Efficient and User-Transparent Hardware Mechanism against ROP Attacks.
ACM Trans. Archit. Code Optim., 2019

Enabling Privacy-Preserving, Compute- and Data-Intensive Computing using Heterogeneous Trusted Execution Environment.
CoRR, 2019

Conditional Speculation: An Effective Approach to Safeguard Out-of-Order Execution Against Spectre Attacks.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

CacheGuard: a security-enhanced directory architecture against continuous attacks.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

NPUFort: a secure architecture of DNN accelerator against model inversion attack.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019

2018
Venice: An Effective Resource Sharing Architecture for Data Center Servers.
ACM Trans. Comput. Syst., 2018

An Efficient Method of Crowd Aggregation Computation in Public Areas.
IEEE Trans. Circuits Syst. Video Technol., 2018

Security-first architecture: deploying physically isolated active security processors for safeguarding the future of computing.
Cybersecur., 2018

Stateful Forward-Edge CFI Enforcement with Intel MPX.
Proceedings of the Advanced Computer Architecture - 12th Conference, 2018

2017
RAGuard: A Hardware Based Mechanism for Backward-Edge Control-Flow Integrity.
Proceedings of the Computing Frontiers Conference, 2017

2016
Venice: Exploring server architectures for effective resource sharing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

P-Socket: optimizing a communication library for a PCIe-based intra-rack interconnect.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
Adapting Memory Hierarchies for Emerging Datacenter Interconnects.
J. Comput. Sci. Technol., 2015

2014
Understanding the behavior of in-memory computing workloads.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
V-OpenCL: a method to use remote GPGPU.
Proceedings of the International Conference on Supercomputing, 2013

The ARMv8 simulator.
Proceedings of the International Conference on Supercomputing, 2013

Cost effective data center servers.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

TCNet: cross-node virtual machine communication acceleration.
Proceedings of the Computing Frontiers Conference, 2013

2012
Micro-architectural characterization of desktop cloud workloads.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

2011
Efficient data streaming with on-chip accelerators: Opportunities and challenges.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011


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