Ruhan A. Conceição

Orcid: 0000-0002-3975-2838

Affiliations:
  • Federal University of Pelotas, Brazil


According to our database1, Ruhan A. Conceição authored at least 22 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Cross-Platform Neural Video Coding: A Case Study.
CoRR, 2024

2020
Complexity and compression efficiency assessment of 3D-HEVC encoder.
Multim. Tools Appl., 2020

High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction.
IEEE Des. Test, 2020

High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
IEEE Des. Test, 2020

2019
Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019

Quality and Energy-Aware HEVC Transrating Based on Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Fast and energy-efficient HEVC transrating based on frame partitioning inheritance.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

LF-CAE: Context-Adaptive Encoding for Lenslet Light Fields Using HEVC.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

2017
Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Video Quality Assessment of Early SKIP/DIS for 3D-HEVC Complexity Reduction.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification.
Proceedings of the 25th European Signal Processing Conference, 2017

2016
Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014
Sample adaptive offset filter hardware design for HEVC encoder.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Configurable hardware design for the HEVC-based Adaptive Loop Filter.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Cost function optimization and its hardware design for the Sample Adaptive Offset of HEVC standard.
Proceedings of the 22nd European Signal Processing Conference, 2014

2013
Hardware design for the 32×32 IDCT of the HEVC video coding standard.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013


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