Ruey-Bin Sheen

According to our database, Ruey-Bin Sheen authored at least 3 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.

Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2020

Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS.

Mao-Hsuan Chou, Ya-Tin Chang, Tsung-Hsien Tsai, Tsung-Che Lu, Chia-Chun Liao, Hung-Yi Kuo, Ruey-Bin Sheen, Chih-Hsien Chang, Kenny C.-H. Hsieh, Alvin Leng Sun Loke, Mark Chen

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2018

A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.

Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018