Ruchir Puri

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Automated Code generation for Information Technology Tasks in YAML through Large Language Models.

[BibT_eX]

[DOI]

CoRR, 2023

Invited: Automated Code generation for Information Technology Tasks in YAML through Large Language Models.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021

Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.

[BibT_eX]

[DOI]

CoRR, 2021

Editorial Introduction.

[BibT_eX]

[DOI]

Neil Yorke-Smith

AI Mag., 2021

Engineering the Future of AI for the Enterprises : Keynote 4.

[BibT_eX]

[DOI]

Proceedings of the IEEE World Congress on Services, 2021

CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks.

[BibT_eX]

[DOI]

Proceedings of the Neural Information Processing Systems Track on Datasets and Benchmarks 1, 2021

2020

Explainable machine learning in deployment.

[BibT_eX]

[DOI]

Proceedings of the FAT* '20: Conference on Fairness, 2020

2019

The Next Generation of Deep Learning Hardware: Analog Computing.

[BibT_eX]

[DOI]

Wilfried Haensch

Tayfun Gokmen

Proc. IEEE, 2019

Model Agnostic Contrastive Explanations for Structured Data.

[BibT_eX]

[DOI]

Karthikeyan Shanmugam

Karthikeyan Natesan Ramamurthy

CoRR, 2019

NeuNetS: An Automated Synthesis Engine for Neural Network Design.

[BibT_eX]

[DOI]

CoRR, 2019

Bias Mitigation Post-processing for Individual and Group Fairness.

[BibT_eX]

[DOI]

Pranay Kr. Lohia

Proceedings of the IEEE International Conference on Acoustics, 2019

2017

Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2017

IBM Deep Learning Service.

[BibT_eX]

[DOI]

Bishwaranjan Bhattacharjee

IBM J. Res. Dev., 2017

IBM Deep Learning Service.

[BibT_eX]

[DOI]

Bishwaranjan Bhattacharjee

CoRR, 2017

2016

Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels.

[BibT_eX]

[DOI]

Robert Karam

Swarup Bhunia

IEEE Trans. Very Large Scale Integr. Syst., 2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Proximity Measure using Blink Model.

[BibT_eX]

[DOI]

CoRR, 2016

2015

Analyzing Analytics

[BibT_eX]

[DOI]

Rajesh Bordawekar

Bob Blainey

Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01749-0, 2015

PARADIS: An Efficient Parallel Algorithm for In-place Radix Sort.

[BibT_eX]

[DOI]

Proc. VLDB Endow., 2015

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

IBM POWER8 circuit design and energy optimization.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2015

IBM z13 circuit design and methodology.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2015

4.1 22nm Next-generation IBM System z microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Message from the program chairs.

[BibT_eX]

[DOI]

Vijay Raghunathan

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Bridging high performance and low power in processor design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Application driven high level design in the era of heterogeneous computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Energy-efficient hardware acceleration through computing in the memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

POWER8 design methodology innovations for improving productivity and reducing power.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automation.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

5.5GHz system z microprocessor and multi-chip module.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Network flow based datapath bit slicing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Opportunities and challenges for high performance microprocessor designs and design automation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Depth controlled symmetric function fanin tree restructure.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Intuitive ECO synthesis for high performance circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2011

Design methodology for the IBM POWER7 microprocessor.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2011

Design, CAD and technology challenges for future processors: 3D perspectives.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

The Dawn of 22nm Era: Design and CAD Challenges.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Logical and physical restructuring of fan-in trees.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Novel binary linear programming for high performance clock mesh synthesis.

[BibT_eX]

[DOI]

Minsik Cho

David Z. Pan

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

EDA challenges and options: investing for the future.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

History-based VLSI legalization using network flow.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Will 22nm be our catch 22!: design and cad challenges.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Symposium on Physical Design, 2009

DeltaSyn: An efficient logic difference optimizer for ECO synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

From milliwatts to megawatts: system level power challenge.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Moore's Law: another casualty of the financial meltdown?

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

64-bit prefix adders: Power-efficient topologies and design solutions.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

CAD challenges for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Placement-Driven Synthesis Design Closure Tool.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Fast Dummy-Fill Density Analysis With Coupling Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Track Routing and Optimization for Yield.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Keeping hot chips cool: are IC thermal problems hot air?

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Custom is from Venus and synthesis from Mars.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Dummy fill density analysis with coupling constraints.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Is your layout density verification exact?: a fast exact algorithm for density calculation.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Physical Design, 2007

Making Manufacturing Work For You.

[BibT_eX]

Srikanth Venkataraman

Proceedings of the 44th Design Automation Conference, 2007

TROY: Track Router with Yield-driven Wire Planning.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Interconnects in the Third Dimension: Design Challenges for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.

[BibT_eX]

[DOI]

Tanay Karnik

Rajiv V. Joshi

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Design and CAD challenges in 45nm CMOS and beyond.

[BibT_eX]

[DOI]

David J. Frank

Dorel Toma

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Wire density driven global routing for CMP variation and timing.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Gain-based technology mapping for minimum runtime leakage under input vector uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

Design of sub-90nm Circuits and Design Methodologies.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Minimizing power with flexible voltage islands.

[BibT_eX]

[DOI]

Leon Stok

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Keeping hot chips cool.

[BibT_eX]

[DOI]

Leon Stok

Subhrajit Bhattacharya

Proceedings of the 42nd Design Automation Conference, 2005

2004

An Integrated Environment for Technology Closure of Deep-Submicron IC Designs.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

2003

Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Design and CAD Challenges in sub-90nm CMOS Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Pushing ASIC performance in a power envelope.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Fast and accurate wire delay estimation for physical synthesis of large ASICs.

[BibT_eX]

[DOI]

Anthony D. Drumm

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001

On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits.

[BibT_eX]

[DOI]

Michael G. Rosenfield

IEEE J. Solid State Circuits, 2001

2000

Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2000

Combinatorial cell design for CMOS libraries.

[BibT_eX]

[DOI]

Integr., 2000

SOI Digital Circuits: Design Issues.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Optimal P/N width ratio selection for standard cell libraries.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

SOI Digital CMOS VLSI - a Design Perspective.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Design issues in mixed static-domino circuit implementations.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1996

A BDD SAT Solver for Satisfiability Testing: An Industrial Case Study.

[BibT_eX]

[DOI]

Ann. Math. Artif. Intell., 1996

Logic optimization by output phase assignment in dynamic logic synthesis.

[BibT_eX]

[DOI]

Andrew Bjorksten

Thomas E. Rosser

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Asynchronous circuit synthesis with Boolean satisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994

A divide-and-conquer approach for asynchronous interface synthesis.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Area Efficient Synthesis of Asynchronous Interface Circuits.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

A Modular Partitioning Approach for Asynchronous Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

1993

Microword length minimization in microprogrammed controller synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

An efficient algorithm to search for minimal closed covers in sequential machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis.

[BibT_eX]

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992

An Efficient algorithm for Microword Length Minimization.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Searching for a minimal finite state automaton (FSA).

[BibT_eX]

[DOI]