Ruby B. Lee

Orcid: 0000-0001-9497-0777

Affiliations:
  • Princeton University, Department of Electrical Engineering, NJ, USA
  • Hewlett-Packard, Cupertino, CA, USA
  • Stanford University, CA, USA (PhD)


According to our database1, Ruby B. Lee authored at least 167 papers between 1989 and 2023.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2001, "For pioneering multimedia instructions in general-purpose processor architecture and innovations in the design and implementation of the instruction set architecture of RISC processors.".

Timeline

Legend:

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Bibliography

2023
Random and Safe Cache Architecture to Defeat Cache Timing Attacks.
CoRR, 2023

Protecting Cache States Against Both Speculative Execution Attacks and Side-channel Attacks.
CoRR, 2023

CloudShield: Real-time Anomaly Detection in the Cloud.
Proceedings of the Thirteenth ACM Conference on Data and Application Security and Privacy, 2023

2021
Attacking and Protecting Data Privacy in Edge-Cloud Collaborative Inference Systems.
IEEE Internet Things J., 2021

CloudShield: Real-time Anomaly Detection in the Cloud.
CoRR, 2021

Smartphone Impostor Detection with Behavioral Data Privacy and Minimalist Hardware Support.
CoRR, 2021

SoK: Hardware Defenses Against Speculative Execution Attacks.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Practical and Scalable Security Verification of Secure Architectures.
Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021

New Models for Understanding and Reasoning about Speculative Execution Attacks.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Speculative Execution Attacks and Hardware Defenses.
Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021

ActionBert: Leveraging User Actions for Semantic Understanding of User Interfaces.
Proceedings of the Thirty-Fifth AAAI Conference on Artificial Intelligence, 2021

2020
Smartphone Impostor Detection with Built-in Sensors and Deep Learning.
CoRR, 2020

Position Paper: Consider Hardware-enhanced Defenses for Rootkit Attacks.
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

2019
Power-Grid Controller Anomaly Detection with Enhanced Temporal Deep Learning.
Proceedings of the 18th IEEE International Conference On Trust, 2019

Sensitive-Sample Fingerprinting of Deep Neural Networks.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

Model inversion attacks against collaborative inference.
Proceedings of the 35th Annual Computer Security Applications Conference, 2019

2018
Design, Implementation and Verification of Cloud Architecture for Monitoring a Virtual Machine's Security Health.
IEEE Trans. Computers, 2018

Special Section on Secure Computer Architectures.
IEEE Trans. Computers, 2018

VerIDeep: Verifying Integrity of Deep Neural Networks through Sensitive-Sample Fingerprinting.
CoRR, 2018

Privacy-preserving Machine Learning through Data Obfuscation.
CoRR, 2018

Detecting Zero-day Controller Hijacking Attacks on the Power-Grid with Enhanced Deep Learning.
CoRR, 2018

Time Series Segmentation through Automatic Feature Learning.
CoRR, 2018

Inferring Smartphone Users' Handwritten Patterns by using Motion Sensors.
Proceedings of the 4th International Conference on Information Systems Security and Privacy, 2018

Record-Replay Architecture as a General Security Framework.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Leveraging Hardware Transactional Memory for Cache Side-Channel Defenses.
Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018

Analyzing Cache Side Channels Using Deep Neural Networks.
Proceedings of the 34th Annual Computer Security Applications Conference, 2018

2017
Cloud Server Benchmark Suite for Evaluating New Hardware Architectures.
IEEE Comput. Archit. Lett., 2017

Blind De-anonymization Attacks using Social Networks.
Proceedings of the 2017 on Workshop on Privacy in the Electronic Society, Dallas, TX, USA, October 30, 2017

Secure Pick Up: Implicit Authentication When You Start Using the Smartphone.
Proceedings of the 22nd ACM on Symposium on Access Control Models and Technologies, 2017

How secure is your cache against side-channel attacks?
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Host-Based Dos Attacks and Defense in the Cloud.
Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017

How to Quantify Graph De-anonymization Risks.
Proceedings of the Information Systems Security and Privacy, 2017

Quantification of De-anonymization Risks in Social Networks.
Proceedings of the 3rd International Conference on Information Systems Security and Privacy, 2017

CloudShelter: Protecting Virtual Machines' Memory Resource Availability in Clouds.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Sensor-Based Implicit Authentication of Smartphone Users.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017

Implicit Smartphone User Authentication with Sensors and Contextual Machine Learning.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2017

Machine Learning Based DDoS Attack Detection from Source Side in Cloud.
Proceedings of the 4th IEEE International Conference on Cyber Security and Cloud Computing, 2017

DoS Attacks on Your Memory in Cloud.
Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security, 2017

2016
State of the Journal.
IEEE Trans. Computers, 2016

Monitoring and Attestation of Virtual Machine Security Health in Cloud Computing.
IEEE Micro, 2016

Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks.
IEEE Micro, 2016

Memory DoS Attacks in Multi-tenant Clouds: Severity and Mitigation.
CoRR, 2016

Cloud Server Benchmarks for Performance Evaluation of New Hardware Architecture.
CoRR, 2016

CloudRadar: A Real-Time Side-Channel Attack Detection System in Clouds.
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2016

Implicit Sensor-based Authentication of Smartphone Users with Smartwatch.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

A hardware-based technique for efficient implicit information flow tracking.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

CATalyst: Defeating last-level cache side channel attacks in cloud computing.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Mapping the Intel Last-Level Cache.
IACR Cryptol. ePrint Arch., 2015

Rethinking Computers for Cybersecurity.
Computer, 2015

Disruptive prefetching: impact on side-channel attacks and cache designs.
Proceedings of the 8th ACM International Systems and Storage Conference, 2015

Last-Level Cache Side-Channel Attacks are Practical.
Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

CloudMonatt: an architecture for security health monitoring and attestation of virtual machines in cloud computing.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Can randomized mapping secure instruction caches from side-channel attacks?
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Implicit Authentication for Smartphone Security.
Proceedings of the Information Systems Security and Privacy, 2015

Multi-sensor Authentication to Improve Smartphone Security.
Proceedings of the ICISSP 2015, 2015

A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Random Fill Cache Architecture.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

HotChips security tutorial.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Security basics.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

University research in hardware security.
Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Cyber defenses for physical attacks and insider threats in cloud computing.
Proceedings of the 9th ACM Symposium on Information, Computer and Communications Security, 2014

New models of cache architectures characterizing information leakage from cache side channels.
Proceedings of the 30th Annual Computer Security Applications Conference, 2014

Hardware-Enhanced Security for Cloud Computing.
Proceedings of the Secure Cloud Computing, 2014

2013
Security Basics for Computer Architects
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01742-1, 2013

Side channel vulnerability metrics: the promise and the pitfalls.
Proceedings of the HASP 2013, 2013

Security testing of a secure cache design.
Proceedings of the HASP 2013, 2013

A Framework for Realizing Security on Demand in Cloud Computing.
Proceedings of the IEEE 5th International Conference on Cloud Computing Technology and Science, 2013

Characterizing hypervisor vulnerabilities in cloud computing servers.
Proceedings of the 2013 International Workshop on Security in Cloud Computing, 2013

BitDeposit: Deterring Attacks and Abuses of Cloud Computing Services through Economic Measures.
Proceedings of the 13th IEEE/ACM International Symposium on Cluster, 2013

2012
Hardware-enhanced access control for cloud computing.
Proceedings of the 17th ACM Symposium on Access Control Models and Technologies, 2012

Security verification of hardware-enabled attestation protocols.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Building Technologies that Help Cyber-Defense: Hardware-enabled Trust.
Proceedings of the ISSE 2012, 2012

Physical attack protection with human-secure virtualization in data centers.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2012

Hardware enhanced security.
Proceedings of the ACM Conference on Computer and Communications Security, 2012

A software-hardware architecture for self-protecting data.
Proceedings of the ACM Conference on Computer and Communications Security, 2012

Architectural support for hypervisor-secure virtualization.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Key Management in Sensor Networks.
Proceedings of the Theoretical Aspects of Distributed Computing in Sensor Networks, 2011

Stability and benefits of suboptimal utility maximization.
IEEE/ACM Trans. Netw., 2011

Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

A Case for Hardware Protection of Guest VMs from Compromised Hypervisors in Cloud Computing.
Proceedings of the 31st IEEE International Conference on Distributed Computing Systems Workshops (ICDCS 2011 Workshops), 2011

Eliminating the hypervisor attack surface for a more secure cloud.
Proceedings of the 18th ACM Conference on Computer and Communications Security, 2011

2010
Processor accelerator for AES.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

NoHype: virtualized cloud infrastructure without the virtualization.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

Scalable architectural support for trusted software.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

General-purpose FPGA platform for efficient encryption and hashing.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

A framework for testing hardware-software security architectures.
Proceedings of the Twenty-Sixth Annual Computer Security Applications Conference, 2010

2009
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines.
Trans. Comput. Sci., 2009

A New Basis for Shifters in General-Purpose Processors for Existing and Advanced Bit Manipulations.
IEEE Trans. Computers, 2009

Securing the Dissemination of Emergency Response Data with an Integrated Hardware-Software Architecture.
Proceedings of the Trusted Computing, 2009

Tuning instruction customisation for reconfigurable system-on-chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Accountability in hosted virtual networks.
Proceedings of the 1st ACM SIGCOMM Workshop on Virtualized Infrastructure Systems and Architectures, 2009

Hardware-Assisted Application-Level Access Control.
Proceedings of the Information Security, 12th International Conference, 2009

Multi-Path Key Establishment against REM Attacks in Wireless Ad Hoc Networks.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Tantra: A Fast PRNG Algorithm and its Implementation.
Proceedings of the 2009 International Conference on Security & Management, 2009

2008
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors.
J. Signal Process. Syst., 2008

Alternative application-specific processor architectures for fast arbitrary bit permutations.
Int. J. Embed. Syst., 2008

Forward-Secure Content Distribution to Reconfigurable Hardware.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A novel cache architecture with enhanced performance and security.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

The Reduced Address Space (RAS) for Application Memory Authentication.
Proceedings of the Information Security, 11th International Conference, 2008

How Bad is Suboptimal Rate Allocation?
Proceedings of the INFOCOM 2008. 27th IEEE International Conference on Computer Communications, 2008

Accelerating the Whirlpool Hash Function Using Parallel Table Lookup and Fast Cyclical Permutation.
Proceedings of the Fast Software Encryption, 15th International Workshop, 2008

Bit matrix multiplication in commodity processors.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Re-examining Probabilistic Versus Deterministic Key Management.
Proceedings of the IEEE International Symposium on Information Theory, 2007

New cache designs for thwarting software cache-based side channel attacks.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Mutual Anonymous Communications: A New Covert Channel Based on Splitting Tree MAC.
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

Secure Key Management Architecture Against Sensor-Node Fabrication Attacks.
Proceedings of the Global Communications Conference, 2007

TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

Hardware-rooted trust for secure key management and transient trust.
Proceedings of the 2007 ACM Conference on Computer and Communications Security, 2007

ISA Support for Fingerprinting and Erasure Codes.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Performing Advanced Bit Manipulations Efficiently in General-Purpose Processors.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

Covert and Side Channels Due to Processor Architecture.
Proceedings of the 22nd Annual Computer Security Applications Conference (ACSAC 2006), 2006

2005
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.
J. VLSI Signal Process., 2005

Protecting cryptographic keys and computations via virtual secure coprocessing.
SIGARCH Comput. Archit. News, 2005

Single-Cycle Bit Permutations with MOMR Execution.
J. Comput. Sci. Technol., 2005

Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

New Constructive Approach to Covert Channel Modeling and Channel Capacity Estimation.
Proceedings of the Information Security, 8th International Conference, 2005

Architecture for Protecting Critical Secrets in Microprocessors.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Capacity Estimation of Non-Synchronous Covert Channels.
Proceedings of the 25th International Conference on Distributed Computing Systems Workshops (ICDCS 2005 Workshops), 2005

On-Chip Lookup Tables for Fast Symmetric-Key Encryption.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

A Traitor Tracing Scheme Based on RSA for Fast Decryption.
Proceedings of the Applied Cryptography and Network Security, 2005

Processor Architecture for Trustworthy Computers.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
On Permutation Operations in Cipher Design.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

PLX FP: an efficient floating-point instruction set for 3D graphics.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Security as a new dimension in embedded system design.
Proceedings of the 41th Design Automation Conference, 2004

Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

Validating Word-Oriented Processors for Bit and Multi-word Operations.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

Distributed Denial of Service: Taxonomies of Attacks, Tools, and Countermeasures.
Proceedings of the ISCA 17th International Conference on Parallel and Distributed Computing Systems, 2004

2003
Architectural techniques for accelerating subword permutations with repetitions.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences.
IEEE Micro, 2003

Enlisting Hardware Architecture to Thwart Malicious Code Injection.
Proceedings of the Security in Pervasive Computing, 2003

Arbitrary Bit Permutations in One or Two Cycles.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Challenges in the Design of Security-Aware Processors.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
PLX: a fully subword-parallel instruction set architecture for fast scalable multimedia processing.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Subword Sorting with Versatile Permutation Instructions.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002

2001
Cryptography Efficient Permutation Instructions for Fast Software.
IEEE Micro, 2001

Multimedia Instructions In IA-64.
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Performance Impact of Addressing Modes on Encryption Algorithms.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Computer Arithmetic-A Processor Architect's Perspective.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
Hardware and software cache prefetching techniques for MPEG benchmarks.
IEEE Trans. Circuits Syst. Video Technol., 2000

Performance Impact of Data Compression on Virtual Private Network Transactions.
Proceedings of the Proceedings 27th Conference on Local Computer Networks, 2000

Cost-effective multiplication with enhanced adders for multimedia applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Fast Subword Permutation Instructions Using Omega and Flip Network Stages.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Bit Permutation Instructions for Accelerating Software Cryptography.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures.
Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1998
An Automated Method for Software Controlled Cache Prefetching.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997
Challenges to Combining General-Purpose and Multimedia Processors.
Computer, 1997

Performance Enhancement of H.263 Encoder Based on Zero Coefficient Prediction.
Proceedings of the Fifth ACM International Conference on Multimedia '97, 1997

An evaluation of video fidelity metrics.
Proceedings of the Proceedings IEEE COMPCON 97, 1997

Image processing considerations for digital photography.
Proceedings of the Proceedings IEEE COMPCON 97, 1997

1996
Guest Editorial: Media processing: a new design target.
IEEE Micro, 1996

Subword parallelism with MAX-2.
IEEE Micro, 1996

A Comparison of Hardware Prefetching Techniques for Mulimedia Benchmarks.
Proceedings of the IEEE International Conference on Multimedia Computing and Systems, 1996

Improving Performance for MPEG Players.
Proceedings of the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, 1996

64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture.
Proceedings of the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, 1996

1995
Algorithmic and architectural enhancements for real-time MPEG-1 decoding on a general purpose RISC workstation.
IEEE Trans. Circuits Syst. Video Technol., 1995

Accelerating multimedia with enhanced microprocessors.
IEEE Micro, 1995

Realtime MPEG Video via Software Decompression oon a PA-RISC Processor.
Proceedings of the COMPCON '95: Technologies for the Information Superhighway, 1995

1989
Precision Architecture.
Computer, 1989


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