Rubin A. Parekhji

According to our database, Rubin A. Parekhji authored at least 71 papers between 1989 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning.

Ayush Arunachalam, Ian Kintz, Suvadeep Banerjee, Arnab Raha, Xiankun Jin, Fei Su, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Suriyaprakash Natarajan, Kanad Basu

CoRR, 2024

Increasing the Efficiency of Hierarchical Fault Simulation through Functional Fault Clustering.

Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Safety-Guided Test Generation for Structural Faults.

Xuanyi Tan, Dhruv Thapar, Deepesh Sahoo, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Rubin A. Parekhji

Proceedings of the IEEE International Test Conference, 2024

Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling.

Tolga Aksoy, Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin A. Parekhji, Sule Ozev

Proceedings of the IEEE European Test Symposium, 2024

Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems.

Sanjay Das, Shamik Kundu, Pooja Madhusoodhanan, Viswanathan Pillai Prasanth, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriya Natarajan, Kanad Basu

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2022

Innovative Practices Track: New Methods for System Level Test of Image Projection and Radar VLSI Systems.

Rubin A. Parekhji

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2021

Exploiting Application Tolerance for Functional Safety.

V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur

Proceedings of the IEEE International Test Conference, 2021

2019

Guest Editorial.

Kanad Basu, Mingsong Chen, Rubin A. Parekhji

J. Electron. Test., 2019

Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis.

V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2018

Towards Single Pin Scan for Extremely Low Pin Count Test.

Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

An optimised SDD ATPG and SDQL computation method across different pattern sets.

Wilson Pradeep, Prakash Narayanan, Rubin A. Parekhji

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Innovative practices session 2C: "How is industry simplifying analog test".

Rubin A. Parekhji, Srinivas Modekurty

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Safety analysis for integrated circuits in the context of hybrid systems.

V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur

Proceedings of the IEEE International Test Conference, 2017

Low cost dynamic error detection in linearity testing of SAR ADCs.

Nimit Jain, Nitin Agarwal, Rajavelu Thinakaran, Rubin A. Parekhji

Proceedings of the IEEE International Test Conference, 2017

2016

A novel technique for interdependent trim code optimization.

Pankaj Bongale, Vinothkumar Sundaresan, Partha Ghosh, Rubin A. Parekhji

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015

Time-Division Multiplexing for Testing DVFS-Based SoCs.

Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs.

Rubin A. Parekhji, Kenneth Butler, Gordon W. Roberts

IEEE Des. Test, 2015

New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation.

V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji

Proceedings of the 28th International Conference on VLSI Design, 2015

On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC.

Osman Emir Erol, Sule Ozev, Chandra K. H. Suresh, Rubin A. Parekhji, Lakshmanan Balasubramanian

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Improved Methods for Accurate Safety Analysis of Real-Life Systems.

V. Prasanth, Rubin A. Parekhji, Bharadwaj S. Amrutur

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Systematic approach for trim test time optimization: Case study on a multi-core RF SOC.

Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji

Proceedings of the 2014 International Test Conference, 2014

Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing.

Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Rubin A. Parekhji, Arvind Jain

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Towards adaptive test of multi-core RF SoCs.

Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Derating based hardware optimizations in soft error tolerant designs.

V. Prasanth, Virendra Singh, Rubin A. Parekhji

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

Proceedings of the 17th IEEE European Test Symposium, 2012

2011

Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.

Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi

J. Low Power Electron., 2011

An efficient test data reduction technique through dynamic pattern mixing across multiple fault models.

Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Multi-CoDec Configurations for Low Power and High Quality Scan Test.

Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management.

Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji

Proceedings of the 2011 IEEE International Test Conference, 2011

Reduced overhead soft error mitigation using error control coding techniques.

V. Prasanth, Virendra Singh, Rubin A. Parekhji

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands.

Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

False Error Vulnerability Study of On-line Soft Error Detection Mechanisms.

M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji

J. Electron. Test., 2010

A generic low power scan chain wrapper for designs using scan compression.

Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Innovative practices session 1C: Innovative practices in RF test.

Rubin A. Parekhji

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Test time reduction using parallel RF test techniques.

Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Robust detection of soft errors using delayed capture methodology.

V. Prasanth, Virendra Singh, Rubin A. Parekhji

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2009

Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test.

Amit Dutta, Malav Shah, G. Swathi, Rubin A. Parekhji

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage.

Hongxia Fang, Krishnendu Chakrabarty, Rubin A. Parekhji

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Low Power Test for Nanometer System-on-Chips (SoCs).

Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena

J. Low Power Electron., 2008

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.

Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A systematic approach to synthesis of verification test-suites for modular SoC designs.

Sudhakar Surendran, Rubin A. Parekhji, R. Govindarajan

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs.

Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji

Proceedings of the 2008 IEEE International Test Conference, 2008

False Error Study of On-line Soft Error Detection Mechanisms.

M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Evaluation of Entropy Driven Compression Bounds on Industrial Designs.

Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Power Analysis and Reduction Techniques for Transition Fault Testing.

Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Modified Stability Checking for On-line Error Detection.

Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Modeling Techniques for Formal Verification of BIST Controllers and Their Integration into SOC Designs.

Subir K. Roy, Rubin A. Parekhji

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs.

Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Methodology for low power test pattern generation using activity threshold control logic.

Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006

Session Abstract.

Rubin A. Parekhji

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

On-chip Test and Repair of Memories for Static and Dynamic Faults.

Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

DFT for Low Cost SOC Test.

Rubin A. Parekhji

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency.

Sameer Goel, Rubin A. Parekhji

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

ITC 2003 panels: Part 1.

Carol Stolicny, Tapio Koivukangas, Rubin A. Parekhji, Ian G. Harris, Rob Aitken

IEEE Des. Test Comput., 2004

Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.

Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.

K. Nikila, Rubin A. Parekhji

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

CESC: a visual formalism for specification and verification of SoCs.

Ambar A. Gadkari, S. Ramesh, Rubin A. Parekhji

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

Testing Embedded Cores and SOCs-DFT, ATPG and BIST Solutions.

Rubin A. Parekhji

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Panel Synopsis - How (In)Adequate is One Time Testing?

Rubin A. Parekhji

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon.

Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000

Test Techniques and Trade-offs for Embedded Cores and Systems.

Rubin A. Parekhji

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx.

Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Functional testing and fault analysis based fault coverage enhancement techniques for embedded core based systems.

Ameet Bagwe, Rubin A. Parekhji

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1996

Monitoring machine based synthesis technique for concurrent error detection in finite state machines.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

J. Electron. Test., 1996

E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation.

Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Concurrent Error Detection Using Monitoring Machines.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

IEEE Des. Test Comput., 1995

A new methodology for the design of low-cost fail safe circuits and networks.

B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1993

State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

Proceedings of the Sixth International Conference on VLSI Design, 1993

1991

A Methodology for Designing Optimal Self-Checking Sequential Circuits.

Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1989

Design methodology and microdiagnostics development for a self-checking microprocessor.

Rubin A. Parekhji, N. K. Nanda

Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989