Ruben W. Castelino

According to our database, Ruben W. Castelino authored at least 3 papers between 1995 and 1997.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1997

Multimedia extensions for a 550-MHz RISC microprocessor.

David A. Carlson, Ruben W. Castelino, Robert O. Mueller

IEEE J. Solid State Circuits, 1997

1995

Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor

John H. Edmondson, Paul I. Rubinfeld, Peter J. Bannon, Bradley J. Benschneider, Debra Bernstein, Ruben W. Castelino, Elizabeth M. Cooper, Daniel E. Dever, Dale R. Donchin, Timothy C. Fischer, Anil K. Jain, Shekhar Mehta, Jeanne E. Meyer, Ronald P. Preston, Vidya Rajagopalan, Chandrasekhara Somanathan, Scott A. Taylor, Gilbert M. Wolrich

Digit. Tech. J., 1995

Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU

William J. Bowhill, Shane L. Bell, Bradley J. Benschneider, Andrew J. Black, Sharon M. Britton, Ruben W. Castelino, Dale R. Donchin, John H. Edmondson, Harry R. Fair III, Paul E. Gronowski, Anil K. Jain, Patricia L. Kroesen, Marc E. Lamere, Bruce J. Loughlin, Shekhar Mehta, Robert O. Mueller, Ronald P. Preston, Sribalan Santhanam, Timothy A. Shedd, Michael J. Smith, Stephen C. Thierauf

Digit. Tech. J., 1995