Roy E. Scheuerlein

According to our database1, Roy E. Scheuerlein authored at least 5 papers between 1988 and 1992.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1988
1989
1990
1991
1992
0
1
2
3
4
3
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1992
A 14-ns 14-Mb CMOS DRAM with 300-mW active power.
IEEE J. Solid State Circuits, September, 1992

A large V/sub DS/ data retention test pattern for DRAM's.
IEEE J. Solid State Circuits, August, 1992

A pulsed sensing scheme with a limited bit-line swing.
IEEE J. Solid State Circuits, April, 1992

1989
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.
IEEE J. Solid State Circuits, October, 1989

1988
Offset word-line architecture for scaling DRAMs to the gigabit level.
IEEE J. Solid State Circuits, February, 1988


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