Roy E. Scheuerlein

According to our database1, Roy E. Scheuerlein authored at least 2 papers between 1988 and 1989.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1989
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.
IEEE J. Solid State Circuits, October, 1989

1988
Offset word-line architecture for scaling DRAMs to the gigabit level.
IEEE J. Solid State Circuits, February, 1988


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