Rourab Paul

According to our database, Rourab Paul authored at least 36 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Blockchain based secret key management for trusted platform module standard in reconfigurable platform.

Rourab Paul, Nimisha Ghosh, Amrutanshu Panigrahi, Amlan Chakrabarti, Prasant Mohapatra

Concurr. Comput. Pract. Exp., October, 2024

FastFlow in FPGA Stacks of Data Centers.

Rourab Paul, Alberto Ottimo, Marco Danelutto

CoRR, 2024

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable Architecture.

Paresh Baidya, Swagata Mandal, Rourab Paul

IEEE Access, 2024

Power Aware Scheduling of Tasks on FPGAs in Data Centers.

Rourab Paul, Marco Danelutto

Proceedings of the 32nd Euromicro International Conference on Parallel, 2024

2023

Smart contract assisted blockchain based public key infrastructure system.

Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul

Trans. Emerg. Telecommun. Technol., January, 2023

2022

HealthCare EHR: A Blockchain-Based Decentralized Application.

Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul

Int. J. Inf. Syst. Supply Chain Manag., 2022

Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture.

Paresh Baidya, Swagata Mandal, Rourab Paul

CoRR, 2022

Smart Contract Assisted Blockchain based PKI System.

Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul

CoRR, 2022

CTB-PKI: Clustering and Trust Enabled Blockchain Based PKI System for Efficient Communication in P2P Network.

Amrutanshu Panigrahi, Ajit Kumar Nayak, Rourab Paul, Bibhuprasad Sahu, Shashi Kant

IEEE Access, 2022

2021

<i>iDCR</i>: Improved Dempster Combination Rule for multisensor fault diagnosis.

Nimisha Ghosh, Sayantan Saha, Rourab Paul

Eng. Appl. Artif. Intell., 2021

Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform.

Rourab Paul, Sreetama Sarkar, Suman Sau, Koushik Chakraborty, Sanghamitra Roy, Amlan Chakrabarti

CoRR, 2021

Blockchain based secure smart city architecture using low resource IoTs.

Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mohapatra

Comput. Networks, 2021

2020

<i>Fault Matters</i>: Sensor data fusion for detection of faults using Dempster-Shafer theory of evidence in IoT-based applications.

Nimisha Ghosh, Rourab Paul, Satyabrata Maity, Krishanu Maity, Sayantan Saha

Expert Syst. Appl., 2020

The Blockchain Based Auditor on Secret key Life Cycle in Reconfigurable Platform.

Rourab Paul, Nimisha Ghosh, Amlan Chakrabarti, Prasant Mahapatra

CoRR, 2020

iDCR: Improved Dempster Combination Rule for Multisensor Fault Diagnosis.

Nimisha Ghosh, Sayantan Saha, Rourab Paul

CoRR, 2020

2019

IoT based Smart Access Controlled Secure Smart City Architecture Using Blockchain.

Rourab Paul, Nimisha Ghosh, Suman Sau, Amlan Chakrabarti, Prasant Mahapatra

CoRR, 2019

Fault Matters: Sensor Data Fusion for Detection of Faults using Dempster-Shafer Theory of Evidence in IoT-Based Applications.

Nimisha Ghosh, Rourab Paul, Satyabrata Maity, Krishanu Maity, Sayantan Saha

CoRR, 2019

2018

Hardware variant NSP with security-aware automated preferential algorithm.

Rourab Paul, Gitesh Sikder, Amlan Chakrabarti, Ranjan Ghosh

IET Comput. Digit. Tech., 2018

Partitioned security processor architecture on FPGA platform.

Rourab Paul, Sandeep K. Shukla

IET Comput. Digit. Tech., 2018

2017

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware.

Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

Microprocess. Microsystems, 2017

A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform.

Rourab Paul, Sandeep Kumar Shukla

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

Multi core SSL/TLS security processor architecture and its FPGA prototype design with automated preferential algorithm.

Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh

Microprocess. Microsystems, 2016

A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code.

Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

IEEE Embed. Syst. Lett., 2016

Accelerating More Secure RC4 : Implementation of Seven FPGA Designs in Stages upto 8 byte per clock.

Rourab Paul, Hemanta Dey, Amlan Chakrabarti, Ranjan Ghosh

CoRR, 2016

Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment.

Jubin Mitra, Shuaib Ahmad Khan, Rourab Paul, Sanjoy Mukherjee, Amlan Chakrabarti, Tapan Kumar Nayak

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2015

A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code.

Swagata Mandal, Rourab Paul, Suman Sau, Amlan Chakrabarti, Subhasis Chattopadhyay

CoRR, 2015

Multicore encryption and authentication on a reconfigurable hardware.

Saheli Ghosh, Subha Jyoti Das, Rourab Paul, Amlan Chakrabarti

Proceedings of the 2nd IEEE International Conference on Recent Trends in Information Systems, 2015

2014

Multi Core SSL/TLS Security Processor Architecture Prototype Design with automated Preferential Algorithm in FPGA.

Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh

CoRR, 2014

Fault Detection for RC4 Algorithm and its Implementation on FPGA Platform.

Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh

CoRR, 2014

Hardware Implementation of four byte per clock RC4 algorithm.

Rourab Paul, Amlan Chakrabarti, Ranjan Ghosh

CoRR, 2014

Performance Evaluation of ECC in Single and Multi Processor Architectures on FPGA Based Embedded System.

Sruti Agarwal, Sangeet Saha, Rourab Paul, Amlan Chakrabarti

CoRR, 2014

2012

A brief experience on journey through hardware developments for image processing and its applications on Cryptography

Sangeet Saha, Chandrajit Pal, Rourab Paul, Satyabrata Maity, Suman Sau

CoRR, 2012

Architecture for real time continuous sorting on large width data volume for fpga based applications

Rourab Paul, Suman Sau, Amlan Chakrabarti

CoRR, 2012

Design and implementation of real time AES-128 on real time operating system for multiple FPGA communication

Rourab Paul, Sangeet Saha, Suman Sau, Amlan Chakrabarti

CoRR, 2012

A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication

Rourab Paul, Sangeet Saha, J. K. M. Sadique Uz Zaman, Suman Das, Amlan Chakrabarti, Ranjan Ghosh

CoRR, 2012

A novel AES-256 implementation on FPGA using co-processor based architecture.

Suman Sau, Rourab Paul, Tanmay Biswas, Amlan Chakrabarti

Proceedings of the 2012 International Conference on Advances in Computing, 2012