Rossella Ranica

According to our database, Rossella Ranica authored at least 6 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration.

R. Berthelon, Olivier Weber, F. Ibars, B. Revel, C. Borowiak, J. C. Grenier, B. Dumont, S. Desmoulins, P. O. Sassoulas, P. Ferreira, S. Chouteau, S. Niel, Rossella Ranica, R. Gonella, Franck Arnaud

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

ASIL-D automotive-grade microcontroller in 28nm FD-SOI with full-OTA capable 21MB embedded PCM memory and highly scalable power management.

Nicolas Grossier, Fabio Disegni, A. Ventre, A. Barcella, R. Mariani, V. Marino, S. Mazzara, A. Scavuzzo, M. Bansal, B. Soni, A. Anand, S. Banzal, D. Joshi, R. Narwal, M. Niranjani, K. Trivedi, P. Ferreira, Rossella Ranica, L. Vullo, Andreia Cathelin, Alfonso Maurelli, S. Pezzini, M. Peri

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021

Improving Ge-rich GST ePCM reliability through BEOL engineering.

Andrea Redaelli, Anna Gandolfo, Giulia Samanni, Enrico Gomiero, Elisa Petroni, Luca Scotti, Andrea Lippiello, Paolo Mattavelli, J. Jasse, D. Codegoni, A. Serafini, Rossella Ranica, Christian Boccaccio, Jury Sandrini, R. Berthelon, J. C. Grenier, Olivier Weber, David Turgis, A. Valery, S. Del Medico, V. Caubet, J. P. Reynard, Didier Dutartre, L. Favennec, Antonino Conte, Fabio Disegni, M. De Tomasi, A. Ventre, Matteo Baldo, Daniele Ielmini, Alfonso Maurelli, P. Ferreira, Franck Arnaud, F. Piazza, Paolo Cappelletti, Roberto Annunziata, R. Gonella

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019

28nm FDSOI Platform with Embedded PCM for IoT, ULP, Digital, Analog, Automotive and others Applications.

Franck Arnaud, Sébastien Haendler, Sylvain Clerc, Rossella Ranica, Anna Gandolfo, Olivier Weber

Proceedings of the 49th European Solid-State Device Research Conference, 2019

2016

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.

Rossella Ranica, Nicolas Planes, Vincent Huard, Olivier Weber, Daniel Noblet, Damien Croain, Fabien Giner, Sylvie Naudet, P. Mergault, S. Ibars, A. Villaret, Maryline Parra, Sébastien Haendler, M. Quoirin, Florian Cacho, C. Julien, F. Terrier, Lorenzo Ciampolini, David Turgis, Christophe Lecocq, Franck Arnaud

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014

Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs.

François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot, Michel Haond

Proceedings of the 44th European Solid State Device Research Conference, 2014