Rosilde Corvino

According to our database1, Rosilde Corvino authored at least 18 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2024
Custom static analysis to enhance insight into the usage of in-house libraries.
J. Syst. Softw., 2024

2017
Extending Halide to Improve Software Development for Imaging DSPs.
ACM Trans. Archit. Code Optim., 2017

Automatic instruction-set architecture synthesis for VLIW processor cores in the ASAM project.
Microprocess. Microsystems, 2017

2014
Construction and exploitation of VLIW ASIPs with heterogeneous vector-widths.
Microprocess. Microsystems, 2014

2013
ASAM: Automatic architecture synthesis and application mapping.
Microprocess. Microsystems, 2013

Hierarchical DSE for multi-ASIP platforms.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Instruction-set architecture exploration strategies for deeply clustered VLIW ASIPs.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

Rapid and accurate energy estimation of vector processing in VLIW ASIPs.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

An Efficient Method for Energy Estimation of Application Specific Instruction-Set Processors.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Exploring processor parallelism: Estimation methods and optimization strategies.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Abstract Clocks for the DSE of Data-Intensive Applications on MPSoCs.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

ASAM: Automatic Architecture Synthesis and Application Mapping.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW Processors.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2010
Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009
Design Space Exploration for data-dominated image applications with non-affine array references. (Exploration de l'espace des architectures pour des systèmes de traitement d'image, analyse faite sur des blocs fondamentaux de la rétine numérique).
PhD thesis, 2009

2008
Automatic generation of a parallel tile processing unit for algorithms with non-affine array references.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008


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