Roshan G. Ragel

Orcid: 0000-0002-4511-2335

Affiliations:
  • University of New South Wales, Sydney, NSW, Australia
  • University of Peradeniya, Sri Lanka (former)


According to our database1, Roshan G. Ragel authored at least 98 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

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Bibliography

2024
S2TPVFormer: Spatio-Temporal Tri-Perspective View for temporally coherent 3D Semantic Occupancy Prediction.
CoRR, 2024

Deep Learning Model for Tamil Part-of-Speech Tagging.
Comput. J., 2024

Multimodal Deep Convolutional Neural Network Pipeline for AI-Assisted Early Detection of Oral Cancer.
IEEE Access, 2024

Comparative Analysis of Pre-trained Deep Neural Networks for Plant Disease Classification.
Proceedings of the 21st International Joint Conference on Computer Science and Software Engineering, 2024

2023
DeepSelectNet: deep neural network based selective sequencing for oxford nanopore sequencing.
BMC Bioinform., December, 2023

Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

Mixed-Reality Based Multi-Agent Robotics Framework for Artificial Swarm Intelligence Experiments.
IEEE Access, 2023

Privacy vs Utility analysis when applying Differential Privacy on Machine Learning Classifiers.
Proceedings of the 19th International Conference on Wireless and Mobile Computing, 2023

A Systematic Approach for Object Detection in Unconstrained Environments.
Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

Enhanced YOLOv4 for Facilitating Public Safety Management amidst Protests and Riots.
Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

RV32IMF Five-Stage Pipeline Implementation with Interrupt and Random Number Generation Units.
Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

Machine Learning based Atmospheric Duct Interference Evaluation in TD-LTE Networks.
Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

CNN for Facial Emotion Recognition in Online Learning Platforms to Identify Learner Engagement.
Proceedings of the 17th IEEE International Conference on Industrial and Information Systems, 2023

2021
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks.
ACM Trans. Design Autom. Electr. Syst., 2021

An Optical Physics Inspired CNN Approach for Intrinsic Image Decomposition.
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021

Part of Speech Tagging for Tamil Language Using Deep Learning.
Proceedings of the 16th International Conference on Industrial and Information Systems, 2021

Suspicious Object Detection in Environments with Tear Gas.
Proceedings of the 16th International Conference on Industrial and Information Systems, 2021

Study of a Switch Architecture for Survivable Routing in Elastic Optical Networks.
Proceedings of the 16th International Conference on Industrial and Information Systems, 2021

2020
Hardware Trojan Mitigation in Pipelined MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2020

FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Framework for Multiple Ground Target Finding and Inspection Using a Multirotor UAS.
Sensors, 2020

A Retinex based GAN Pipeline to Utilize Paired and Unpaired Datasets for Enhancing Low Light Images.
CoRR, 2020

Wikidata based Location Entity Linking.
Proceedings of the 9th International Conference on Software and Computer Applications, 2020

2019
An Ensemble Learning Approach for Electrocardiogram Sensor Based Human Emotion Recognition.
Sensors, 2019

Optical Character Translation Using Spectacles (OCTS).
Proceedings of the 14th Conference on Industrial and Information Systems, 2019

Named Entity Extraction of Wikidata Items.
Proceedings of the 14th Conference on Industrial and Information Systems, 2019

Non-contact Infant Sleep Apnea Detection.
Proceedings of the 14th Conference on Industrial and Information Systems, 2019

Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific Testing.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
An optimized Parallel Failure-less Aho-Corasick algorithm for DNA sequence matching.
CoRR, 2018

To Use or Not to Use: CPUs' Cache Optimization Techniques on GPGPUs.
CoRR, 2018

Near Real-Time Data Labeling Using a Depth Sensor for EMG Based Prosthetic Arms.
Proceedings of the Intelligent Systems and Applications, 2018

2017
Burst switching using variable optical splitter based switches with wavelength conversion.
Proceedings of the 2017 IEEE International Conference on Industrial and Information Systems, 2017

Separating tables from text and non-text objects in printed documents for digital reconstruction.
Proceedings of the 2017 IEEE International Conference on Industrial and Information Systems, 2017

Implementing a proven-secure and cost-effective countermeasure against the compression ratio info-leak mass exploitation (CRIME) attack.
Proceedings of the 2017 IEEE International Conference on Industrial and Information Systems, 2017

TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs.
Proceedings of the 54th Annual Design Automation Conference, 2017

DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016
Switchable cache: utilising dark silicon for application specific cache optimisations.
IET Comput. Digit. Tech., 2016

Processor Design for Soft Errors: Challenges and State of the Art.
ACM Comput. Surv., 2016

2015
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

SecureD: A Secure Dual Core Embedded Processor.
CoRR, 2015

Side channel attacks in embedded systems: A tale of hostilities and deterrence.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

RotateCAPTCHA a novel interactive CAPTCHA design targeting mobile devices.
Proceedings of the 10th IEEE International Conference on Industrial and Information Systems, 2015

Pre-configured backup protection with limited resource sharing in elastic optical networks.
Proceedings of the 10th IEEE International Conference on Industrial and Information Systems, 2015

Accelerating text-based plagiarism detection using GPUs.
Proceedings of the 10th IEEE International Conference on Industrial and Information Systems, 2015

The A to Z of building a testbed for Power Analysis attacks.
Proceedings of the 10th IEEE International Conference on Industrial and Information Systems, 2015

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
A Structured Hardware Software Architecture for Peptide Based Diagnosis - Sub-string Matching Problem with Limited Tolerance (ICIAfS14).
CoRR, 2014

A Structured Hardware Software Architecture for Peptide Based Diagnosis of Baylisascaris Procyonis Infection (ICIAfS14).
CoRR, 2014

Tile optimization for area in FPGA based hardware acceleration of peptide identification.
CoRR, 2014

Hardware accelerated protein inference framework.
CoRR, 2014

Hardware software co-design of the Aho-Corasick algorithm: Scalable for protein identification?
CoRR, 2014

To Use or Not to Use: Graphics Processing Units for Pattern Matching Algorithms.
CoRR, 2014

Efficient Switch Architectures for Pre-configured Backup Protection with Sharing in Elastic Optical Networks (EON).
CoRR, 2014

Register Spilling for Specific Application Domains in Application Specific Instruction-set Processors.
CoRR, 2014

Students Behavioural Analysis in an Online Learning Environment Using Data Mining (ICIAfS).
CoRR, 2014

Instruction-set Selection for Multi-application based ASIP Design: An Instruction-level Study.
CoRR, 2014

Authorship detection of SMS messages using unigrams.
CoRR, 2014

Accelerating motif finding in DNA sequences with multicore CPUs.
CoRR, 2014

Heterogeneous processor pipeline for a product cipher application.
CoRR, 2014

Loop Unrolling in Multi-pipeline ASIP Design.
CoRR, 2014

Locating Tables in Scanned Documents for Reconstructing and Republishing (ICIAfS14).
CoRR, 2014

User Friendly Line CAPTCHAs.
CoRR, 2014

AntiPlag: Plagiarism Detection on Electronic Submissions of Text Based Assignments.
CoRR, 2014

Plagiarism Detection on Electronic Text based Assignments using Vector Space Model (ICIAfS14).
CoRR, 2014

Constant time encryption as a countermeasure against remote cache timing attacks.
CoRR, 2014

Accelerating string matching for bio-computing applications on multi-core CPUs.
CoRR, 2014

Software implementation level countermeasures against the cache timing attack on advanced encryption standard.
CoRR, 2014

A Fuzzy Based Model to Identify Printed Sinhala Characters (ICIAfS14).
CoRR, 2014

Accelerating Correlation Power Analysis Using Graphics Processing Units.
CoRR, 2014

LineCAPTCHA Mobile: A User Friendly Replacement for Unfriendly Reverse Turing Tests for Mobile Devices (ICIAfS14).
CoRR, 2014

Improving the throughput of the AES algorithm with multicore processors.
CoRR, 2014

Axis2UNO: Web Services Enabled Openoffice.org.
CoRR, 2014

String Matching with Multicore CPUs: Performing Better with the Aho-Corasick Algorithm.
CoRR, 2014

Countermeasures against Bernstein's remote cache timing attack.
CoRR, 2014

A Feasibility Study on Programmer Specific Instruction Set Processors (PSISPs).
CoRR, 2014

Advanced modes in AES: Are they safe from power analysis based side channel attacks?
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
High Throughput Virtual Screening with Data Level Parallelism in Multi-core Processors.
CoRR, 2013

A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

DRMA: dynamically reconfigurable MPSoC architecture.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A novel intermittent fault Markov model for deep sub-micron processors.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
Proceedings of the Design, Automation and Test in Europe, 2013

Machine learning based search space optimisation for drug discovery.
Proceedings of the 2013 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology (CIBCB), 2013

2012
Randomized Instruction Injection to Counter Power Analysis Attacks.
ACM Trans. Embed. Comput. Syst., 2012

Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Architectural Frameworks for Security and Reliability of MPSoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A hybrid hardware-software technique to improve reliability in embedded processors.
ACM Trans. Embed. Comput. Syst., 2011

Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks.
IET Comput. Digit. Tech., 2011

A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks.
Proceedings of the IEEE 10th International Conference on Trust, 2011

2010
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.
Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

2009
Security and Dependability of Embedded Systems: A Computer Architects' Perspective.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

CUFFS: An instruction count based architectural framework for security of MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

2007
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks.
Proceedings of the 44th Design Automation Conference, 2007

A smart random code injection to mask power analysis based side channel attacks.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Architectural support for security and reliability in embedded processors.
PhD thesis, 2006

IMPRES: integrated monitoring for processor reliability and security.
Proceedings of the 43rd Design Automation Conference, 2006

Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Micro embedded monitoring for security in application specific instruction-set processors.
Proceedings of the 2005 International Conference on Compilers, 2005


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