Rose George Kunthara

Orcid: 0000-0001-5376-5718

According to our database1, Rose George Kunthara authored at least 11 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Subnetwork Based Traffic Aware Rerouting for CMesh Bufferless Network-on-Chip.
J. Circuits Syst. Comput., August, 2024

2023
Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks.
SN Comput. Sci., May, 2023

Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022
RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Traffic aware routing in 3D NoC using interleaved asymmetric edge routers.
Nano Commun. Networks, 2021

Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

2019
2L-2D Routing for Buffered Mesh Network-on-Chip.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip.
Proceedings of the TENCON 2019, 2019

Asymmetric routing in 3D NoC using interleaved edge routers.
Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

2018
ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018


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