Ronny Morad

According to our database1, Ronny Morad authored at least 17 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
Post-Silicon Validation in the SoC Era: A Tutorial Introduction.
IEEE Des. Test, 2017

Cost-effective analysis of post-silicon functional coverage events.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Unveiling difficult bugs in address translation caching arrays for effective post-silicon validation.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Solutions to IBM POWER8 verification challenges.
IBM J. Res. Dev., 2015

2014
ArChiVED: Architectural checking via event digests for high performance validation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Panel: Future SoC verification methodology: UVM evolution or revolution?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

SLAM: SLice And Merge - Effective Test Generation for Large Systems.
Proceedings of the Hardware and Software: Verification and Testing, 2013

2012
Approximating checkers for simulation acceleration.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Accelerators and emulators: Can they become the platform of choice for hardware verification?
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Checking architectural outputs instruction-by-instruction on acceleration platforms.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Facing the challenge of new design features: an effective verification approach.
Proceedings of the 48th Design Automation Conference, 2011

2010
Ontology-Based Tools in the Service of Hardware Verification.
Proceedings of the 22nd International Conference on Software Engineering & Knowledge Engineering (SEKE'2010), Redwood City, San Francisco Bay, CA, USA, July 1, 2010

Special Session on Debugging.
Proceedings of the Hardware and Software: Verification and Testing, 2010

2008
IBM system z functional and performance verification using X-Gen.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008


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