Rongliang Fu

Orcid: 0000-0003-3744-2083

According to our database1, Rongliang Fu authored at least 12 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array.
Proceedings of the 53rd International Conference on Parallel Processing, 2024

JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits.
IEEE Trans. Computers, 2022

A survey on superconducting computing technology: circuits, architectures and design tools.
CCF Trans. High Perform. Comput., 2022

2021
Equivalence Checking for Superconducting RSFQ Logic Circuits.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020


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