Rongjian Liang

Orcid: 0000-0001-8626-2359

According to our database1, Rongjian Liang authored at least 23 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
GOALPlace: Begin with the End in Mind.
CoRR, 2024

OpenROAD and CircuitOps: Infrastructure for ML EDA Research and Education.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

Learning to Compare Hardware Designs for High-Level Synthesis.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner.
Proceedings of the 2024 International Symposium on Physical Design, 2024

GPU/ML-Enhanced Large Scale Global Routing Contest.
Proceedings of the 2024 International Symposium on Physical Design, 2024

DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

DGR: Differentiable Global Router.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
ChipNeMo: Domain-Adapted LLMs for Chip Design.
CoRR, 2023

Invited Paper: CircuitOps: An ML Infrastructure Enabling Generative AI for VLSI Circuit Optimization.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

BufFormer: A Generative ML Framework for Scalable Buffering.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Preplacement Net Length and Timing Estimation by Customized Graph Neural Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Mapping Large Scale Finite Element Computing on to Wafer-Scale Engines.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge Transfer.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Automatic Routability Predictor Development Using Neural Architecture Search.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Virtual-joint based motion similarity criteria for human-robot kinematics mapping.
Robotics Auton. Syst., 2020

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

Routing-Free Crosstalk Prediction.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020


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