Rong Lin
According to our database1,
Rong Lin
authored at least 57 papers
between 1989 and 2024.
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Bibliography
2024
The differences in gastric cancer epidemiological data between SEER and GBD: a joinpoint and age-period-cohort analysis.
J. Big Data, December, 2024
2023
Prediction of solar wind speed by applying convolutional neural network to potential field source surface (PFSS) magnetograms.
CoRR, 2023
2022
Research on the precise employment model of college students from the perspective of competency.
Proceedings of the 18th International Conference on Computational Intelligence and Security, 2022
2021
Contrastive Learning Framework by Maximizing Mutual Information for Visual Question Answering.
Proceedings of the 2021 International Conference on Security, 2021
2020
Effects of Commensurability on the Friction and Energy Dissipation in Graphene/Graphene Interface.
Proceedings of the 15th IEEE International Conference on Nano/Micro Engineered and Molecular System, 2020
2016
Application research of the power line carrier communication multiband based on G3 technology.
Proceedings of the 3rd International Conference on Systems and Informatics, 2016
2005
An Empirical Study on the Specification and Selection of Components Using Fuzzy Logic.
Proceedings of the Component-Based Software Engineering, 8th International Symposium, 2005
2003
IEEE Trans. Parallel Distributed Syst., 2003
A Reconfigurable Low-Power High-Performance Matrix Multiplier Architecture with Borrow Parallel Counters.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
2002
Bit-Matrix Decomposition and Dynamic Reconfiguration: A Unified Arithmetic Processor Architecture, Design and Test.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Novel design and verification of a 16 x 16-b self-repairable reconfigurable inner product processor.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
2001
A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits.
VLSI Design, 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Inner Product Processor Designs Using High-Performance, Non-Binary Logic Circuits.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001
2000
IEEE Trans. Parallel Distributed Syst., 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the Parallel and Distributed Processing, 2000
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Parallel Distributed Syst., 1999
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
1997
Reconfigurable buses with shift switches for fast final additions of parallel multipliers.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997
Proceedings of the Fourth International on High-Performance Computing, 1997
1995
IEEE Trans. Parallel Distributed Syst., 1995
Parallel Algorithms Appl., 1995
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995
1994
Parallel Process. Lett., 1994
Parallel Algorithms Appl., 1994
J. Parallel Distributed Comput., 1994
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
Convolution Computation on Shift Switching Buses.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Proceedings of the International Conference on Application-Specific Array Processors, 1993
1992
Parallel Comput., 1992
Reconfigurable Buses with Shift Switching - VLSI RADIX Sort.
Proceedings of the 1992 International Conference on Parallel Processing, 1992
Proceedings of the Parallel Processing: CONPAR 92, 1992
1991
Fast Algorithms for Lowest Common Ancestors on a Processor Array with Reconfigurable Buses.
Inf. Process. Lett., 1991
A Fast Parallel Algorithm to Compute Path Functions for Cographs.
Proceedings of the International Conference on Parallel Processing, 1991
Proceedings of the Advances in Computing and Information, 1991
Proceedings of the 19th annual conference on Computer Science, 1991
1990
Inf. Process. Lett., 1990
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990
Proceedings of the Next Decade in Information Technology: Proceedings of the 5th Jerusalem Conference on Information Technology 1990, 1990
Proceedings of the Foundations of Software Technology and Theoretical Computer Science, 1990
1989
A Classification Approach for Automated Reasoning Systems-A Case Study in Graph Theory.
PhD thesis, 1989