Rong-Jyi Yang
According to our database1,
Rong-Jyi Yang
authored at least 13 papers
between 2004 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2015
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2012
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
IEEE J. Solid State Circuits, 2007
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm.
IEEE J. Solid State Circuits, 2007
2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE J. Solid State Circuits, 2006
2005
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector.
IEICE Trans. Electron., 2005
IEICE Trans. Electron., 2005
2004
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE J. Solid State Circuits, 2004