Ronald D. Fellman

According to our database1, Ronald D. Fellman authored at least 14 papers between 1990 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

1996
Successive Superposition: A Technique for the Exact Modeling of Deterministic Packet Queuing Networks.
IEEE Trans. Parallel Distributed Syst., 1996

An extension to the SCI flow control protocol for increased network efficiency.
IEEE/ACM Trans. Netw., 1996

An efficient adaptive input quantizer for resetable dynamic robotic systems.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

1995
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems.
J. VLSI Signal Process., 1995

A VLSI priority packet queue with inheritance and overwrite.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Macro pipelining based scheduling on high performance heterogeneous multiprocessor systems.
IEEE Trans. Signal Process., 1995

An implementation efficient learning algorithm for adaptive control using associative content addressable memory.
IEEE Trans. Syst. Man Cybern., 1995

The effect of preemptive queuing in a priority-based real-time network.
Proceedings of the 1st IEEE International Conference on Engineering of Complex Computer Systems (ICECCS '95), 1995

1994
Scaling and Performance of a Priority Packet Queue for Real-Time Applications.
Proceedings of the 15th IEEE Real-Time Systems Symposium (RTSS '94), 1994

A VLSI Priority Packet Queue with Overwrite and Inheritance.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Enhancing SCI's fairness protocol for increased throughput.
Proceedings of the 1993 International Conference on Network Protocols, 1993

1992
Macropipelining based heterogeneous multiprocessor scheduling.
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

1990
Design and evaluation of an architecture for a digital signal processor for instrumentation applications.
IEEE Trans. Acoust. Speech Signal Process., 1990

Design issues and an architecture for the monolithic implementation of a parallel digital signal processor.
IEEE Trans. Acoust. Speech Signal Process., 1990


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