Ron Press

Orcid: 0000-0001-6855-0568

According to our database1, Ron Press authored at least 11 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2024
Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs.
Proceedings of the IEEE International Test Conference, 2024

2017
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
ITC and the Future of Test - We've Won.
IEEE Des. Test, 2016

2010
The ABCs of ITC.
IEEE Des. Test Comput., 2010

2009
Scan Compression Implementation in Industrial Design - Case Study.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2006
The Demand and Practical Approach for 100x Test Compression.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Mentor Graphics DFT to Navigate Nanometer Test Challenges.
Proceedings of the 15th Asian Test Symposium, 2006

2005
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
Proceedings of the 2005 Design, 2005

Achieving High Test Quality with Reduced Pin Count Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003
High-Frequency, At-Speed Scan Testing.
IEEE Des. Test Comput., 2003


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