Ron Press
Orcid: 0000-0001-6855-0568
According to our database1,
Ron Press
authored at least 11 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs.
Proceedings of the IEEE International Test Conference, 2024
2017
Automotive IC On-line Test Techniques and the Application of Deterministic ATPG-Based Runtime Test.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
2010
2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
Proceedings of the 2005 Design, 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2003