Roman Gauchi

According to our database, Roman Gauchi authored at least 10 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Secure eFPGA Configuration: A System-Level Approach.

Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures.

Aurélien Alacchi, Edouard Giacomin, Roman Gauchi, Szymon Kulis, Pierre-Emmanuel Gaillardon

IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking.

Aurélien Alacchi, Edouard Giacomin, Scott Temple, Roman Gauchi, Michael J. Wirthlin, Pierre-Emmanuel Gaillardon

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

2022

Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution.

Maha Kooli, Antoine Heraud, Henri-Pierre Charles, Bastien Giraud, Roman Gauchi, Mona Ezzadeen, Kevin Mambu, Valentin Egloff, Jean-Philippe Noel

ACM J. Emerg. Technol. Comput. Syst., 2022

An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing.

Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis.

Roman Gauchi, Ashton Snelgrove, Pierre-Emmanuel Gaillardon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.

Valentin Egloff, Jean-Philippe Noel, Maha Kooli, Bastien Giraud, Lorenzo Ciampolini, Roman Gauchi, César Fuguet Tortolero, Eric Guthmuller, Mathieu Moreau, Jean-Michel Portal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization.

Roman Gauchi, Valentin Egloff, Maha Kooli, Jean-Philippe Noël, Bastien Giraud, Pascal Vivet, Subhasish Mitra, Henri-Pierre Charles

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing.

Jean-Philippe Noël, Valentin Egloff, Maha Kooli, Roman Gauchi, Jean-Michel Portal, Henri-Pierre Charles, Pascal Vivet, Bastien Giraud

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture.

Roman Gauchi, Maha Kooli, Pascal Vivet, Jean-Philippe Noël, Edith Beigné, Subhasish Mitra, Henri-Pierre Charles

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019