Romain Ritzenthaler
According to our database1,
Romain Ritzenthaler
authored at least 22 papers
between 2012 and 2024.
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Bibliography
2024
DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations.
Proceedings of the IEEE International Memory Workshop, 2022
2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
2019
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process.
Proceedings of the European Solid-State Device Research Conference, 2013
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Proceedings of the 2012 European Solid-State Device Research Conference, 2012