Rolf Sautter

According to our database1, Rolf Sautter authored at least 6 papers between 2001 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2017
A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2015
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.
Proceedings of the ESSCIRC Conference 2015, 2015

2010
A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


2005
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2001
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core.
IEEE J. Solid State Circuits, 2001


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