Rohit Kapur

According to our database, Rohit Kapur authored at least 86 papers between 1991 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

New scan compression approach to reduce the test data volume.

Pralhadrao V. Shantagiri, Rohit Kapur, Chandrasekar Shastry

IET Comput. Digit. Tech., 2021

2020

A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits.

Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2018

Handling Unknown with Blend of Scan and Scan Compression.

Pralhadrao V. Shantagiri, Rohit Kapur

J. Electron. Test., 2018

Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits.

Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur

CoRR, 2018

2017

A New Logic Encryption Strategy Ensuring Key Interdependency.

Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Deterministic Shift Power Reduction in Test Compression.

Kanad Basu, Rishi Kumar, Santosh Kulkarni, Rohit Kapur

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set.

Subhadip Kundu, Kuldip Kumar, Rishi Kumar, Rohit Kapur

Proceedings of the IEEE International Test Conference, 2017

Enhancing security of logic encryption using embedded key generation unit.

Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur

Proceedings of the International Test Conference in Asia, 2017

2016

Small Test Set Generation with High Diagnosability.

Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

J. Circuits Syst. Comput., 2016

Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors.

Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur

Proceedings of the 2016 IEEE International Test Conference, 2016

2015

Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment.

Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

IEEE Trans. Very Large Scale Integr. Syst., 2015

Designing efficient combinational compression architecture for testing industrial circuits.

Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

GA based diagnostic test pattern generation for transition faults.

Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Designing effective scan compression solutions for industrial circuits.

Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Fault diagnosis in designs with extreme low pin test data compressors.

Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.

Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

IEEE Trans. Very Large Scale Integr. Syst., 2014

Innovative practices session 10C: Advances in DFT and compression.

Rohit Kapur, Irith Pomeranz

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Unifying scan compression.

Swapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A Case Study on Implementing Compressed DFT Architecture.

Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A Metric for Test Set Characterization and Customization Toward Fault Diagnosis.

Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Aggresive scan chain masking for improved diagnosis of multiple scan chain failures.

Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

Proceedings of the 18th IEEE European Test Symposium, 2013

An ATE assisted DFD technique for volume diagnosis of scan chains.

Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection.

Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

Special session 5B: Panel How much toggle activity should we be testing with?

Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.

Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Predicting Scan Compression IP Configurations for Better QoR.

Jyotirmoy Saikia, Pramod Notiyath, Santosh Kulkarni, Ashok Anbalan, Rajesh Uppuluri, Tammy Fernandes, Parthajit Bhattacharya, Rohit Kapur

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C).

Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur

Proceedings of the 20th IEEE Asian Test Symposium, 2011

3D-Scalable Adaptive Scan (3D-SAS).

Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Conference Reports.

Rohit Kapur

IEEE Des. Test Comput., 2010

2009

CTL and Its Usage in the EDA Industry.

Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller

IEEE Des. Test Comput., 2009

Proactive management of X's in scan chains for compression.

Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Scalable Adaptive Scan (SAS).

Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Historical Perspective on Scan Compression.

Rohit Kapur, Subhasish Mitra, Thomas W. Williams

IEEE Des. Test Comput., 2008

Bounded Adjacent Fill for Low Capture Power Scan Testing.

Anshuman Chandra, Rohit Kapur

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Interval Based X-Masking for Scan Compression Architectures.

Anshuman Chandra, Rohit Kapur

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction.

Anshuman Chandra, Felix Ng, Rohit Kapur

Proceedings of the Design, Automation and Test in Europe, 2008

Not All Xs are Bad for Scan Compression.

Anshuman Chandra, Rohit Kapur

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Evaluation of Entropy Driven Compression Bounds on Industrial Designs.

Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

DFT MAX and Power.

Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri

J. Low Power Electron., 2007

Minimizing the Impact of Scan Compression.

Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction.

Anshuman Chandra, Haihua Yan, Rohit Kapur

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fundamentals of timing information for test: How simple can we get?

Rohit Kapur, Jindrich Zejda, Thomas W. Williams

Proceedings of the 2007 IEEE International Test Conference, 2007

Accurately Determining Bridging Defects from Layout.

Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Testing in the year 2020.

Rajesh Galivanche, Rohit Kapur, Antonio Rubio

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

OCI: Open Compression Interface.

Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Efficient compression of deterministic patterns into multiple PRPG seeds.

Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Test the test experts: do we know what we are doing?

Rohit Kapur

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

Changing the Scan Enable during Shift.

Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Security vs. Test Quality: Are they mutually exclusive?

Rohit Kapur

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Speed Binning with Path Delay Test in 150-nm Technology.

Bruce Cory, Rohit Kapur, Bill Underwood

IEEE Des. Test Comput., 2003

A Reconfigurable Shared Scan-in Architecture.

Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Overview of the IEEE P1500 Standard.

Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture.

Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch

Proceedings of the 2003 Design, 2003

2002

On IEEE P1500's Standard for Embedded Core Test.

Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian

J. Electron. Test., 2002

Dynamic Scan: Driving Down the Cost of Test.

Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams

Computer, 2002

Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme.

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Integrating DFT in the Physical Synthesis Flow.

Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fast seed computation for reseeding shift register in test pattern compression.

Nahmsuk Oh, Rohit Kapur, Thomas W. Williams

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Directed-Binary Search in Logic BIST Diagnostics.

Rohit Kapur, Thomas W. Williams, M. Ray Mercer

Proceedings of the 2002 Design, 2002

Enhancing test efficiency for delay fault testing using multiple-clocked schemes.

Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams

Proceedings of the 39th Design Automation Conference, 2002

Manufacturing Test of SoCs.

Rohit Kapur, Thomas W. Williams

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Strategies for Low-Cost Test.

Rohit Kapur, R. Chandramouli, Thomas W. Williams

IEEE Des. Test Comput., 2001

IP and Automation to Support IEEE P1500.

Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

A new methodology for improved tester utilization.

Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Tester retargetable patterns.

Rohit Kapur, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

CTL the language for describing core-based test.

Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

The Mutating Metric for Benchmarking Test.

Rohit Kapur, Cy Hay, Thomas W. Williams

IEEE Des. Test Comput., 2000

On using IEEE P1500 SECT for test plug-n-play.

Yervant Zorian, Erik Jan Marinissen, Rohit Kapur

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Design for Testability in Nanometer Technologies; Searching for Quality.

Thomas W. Williams, Rohit Kapur

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

DFT closure.

Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction.

Rohit Kapur, Thomas W. Williams

Computer, 1999

Towards a standard for embedded core test: an example.

Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

High level ATPG is important and is on its way!

Rohit Kapur

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997

Cost-Driven Ranking of Memory Elements for Partial Intrusion.

Magdy S. Abadir, Rohit Kapur

IEEE Des. Test Comput., 1997

1996

A weighted random pattern test generation system.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction).

Rohit Kapur, Edward F. Miller

Computer, 1996

I_DDQ Test: Sensitivity Analysis of Scaling.

Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Iddq Testing for High Performance CMOS - The Next Ten Years.

Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly

Proceedings of the 1996 European Design and Test Conference, 1996

1994

Limitations in predicting defect level based on stuck-at fault coverage.

Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Design of an Efficient Weighted-Random-Pattern Generation System.

Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1992

Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes.

Rohit Kapur, M. Ray Mercer

IEEE Trans. Computers, 1992

The roles of controllability and observability in design for test.

Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

All Tests for a Fault Are Not Equally Valuable for Defect Detection.

Rohit Kapur, Jaehong Park, M. Ray Mercer

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Functional Approaches to Generating Orderings for Efficient Symbolic Representations.

M. Ray Mercer, Rohit Kapur, Don E. Ross

Proceedings of the 29th Design Automation Conference, 1992

1991

Fast functional evaluation of candidate OBDD variable orderings.

Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer

Proceedings of the conference on European design automation, 1991

Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams.

Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer

Proceedings of the 28th Design Automation Conference, 1991