Rohan Sinha

Orcid: 0000-0002-3606-7181

According to our database1, Rohan Sinha authored at least 19 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Unpacking Failure Modes of Generative Policies: Runtime Monitoring of Consistency and Progress.
CoRR, 2024

Adapting a Foundation Model for Space-based Tasks.
CoRR, 2024

Real-Time Anomaly Detection and Reactive Planning with Large Language Models.
CoRR, 2024

Learning Temporal Logic Predicates from Data with Statistical Guarantees.
CoRR, 2024

Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic Body Biasing Scheme.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Online Distribution Shift Detection via Recency Prediction.
Proceedings of the IEEE International Conference on Robotics and Automation, 2024

2023
Semantic anomaly detection with large language models.
Auton. Robots, December, 2023

A Temperature Compensated Voltage Controlled Relaxation Oscillator for Frequency Modulated DC-DC Charge Pump Regulation.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

Closing the Loop on Runtime Monitors with Fallback-Safe MPC.
Proceedings of the 62nd IEEE Conference on Decision and Control, 2023

2022
A System-Level View on Out-of-Distribution Data in Robotics.
CoRR, 2022

Adaptive Robust Model Predictive Control via Uncertainty Cancellation.
CoRR, 2022

Online Distribution Shift Detection via Recency Prediction.
CoRR, 2022

An Accurate Modelling of CMOS Folded Cascode Op-Amp with Negative Transconductance.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Adaptive Robust Model Predictive Control with Matched and Unmatched Uncertainty.
Proceedings of the American Control Conference, 2022

2020
A 0.8V Input Charge Pump Circuit with PVT Aware Body Bias Clock Drivers for Powering Non-Volatile Memories.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2018
Stress Relaxed Multiple Output High-Voltage Level Shifter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

2015
Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A new row decoding architecture for fast wordline charging in NOR type Flash memories.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
A positive level shifter for high speed symmetric switching in flash memories.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014


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