Rohan Juneja

According to our database, Rohan Juneja authored at least 10 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.

Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

Proceedings of the 36th IEEE Hot Chips Symposium, 2024

NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator.

Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong, Li-Shiuan Peh

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML.

Pranav Dangi, Zhenyu Bai, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra

Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023

BioThings Explorer: a query engine for a federated knowledge graph of biomedical APIs.

Jackson Callaghan, Colleen H. Xu, Jiwen Xin, Marco Alvarado Cano, Anders Riutta, Eric Zhou, Rohan Juneja, Yao Yao, Madhumita Narayan, Kristina Hanspers, Ayushi Agrawal, Alexander R. Pico, Chunlei Wu, Andrew I. Su

Bioinform., September, 2023

FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.

Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables.

Mohit Upadhyay, Rohan Juneja, Bo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication.

Saru Vig, Siew-Kei Lam, Rohan Juneja

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

DISSECT: Dynamic Skew-and-Split Tree for Memory Authentication.

Saru Vig, Rohan Juneja, Siew-Kei Lam

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree.

Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew-Kei Lam, Changhai Ou

IEEE Trans. Very Large Scale Integr. Syst., 2019

2018

Dynamic NoC platform for varied application needs.

Sidhartha Sankar Rout, Hemanta Kumar Mondal, Rohan Juneja, Sri Harsha Gade, Sujay Deb

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018