Roghayeh Saeidi

According to our database, Roghayeh Saeidi authored at least 24 papers between 2005 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

KAZE-SAR: SAR Image Registration Using KAZE Detector and Modified SURF Descriptor for Tackling Speckle Noise.

Mohammadreza Pourfard, Tahmineh Hosseinian, Roghayeh Saeidi, Sayed Ahmad Motamedi, Mohammad Javad Abdollahifard, Reza Mansoori, Reza Safabakhsh

IEEE Trans. Geosci. Remote. Sens., 2022

Accurate and Insightful Closed-Form Prediction of Subthreshold SRAM Hold Failure Rate.

Léopold Van Brandt, Roghayeh Saeidi, David Bol, Denis Flandre

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021

SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode.

David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre

IEEE J. Solid State Circuits, 2021

Hardware Trojan Prevention and Detection by Filling Unused Space Using Shift registers, Gate-chain and Extra Routing.

Mansoureh Labbafniya, Shahram Etemadi Borujeni, Roghayeh Saeidi

ISC Int. J. Inf. Secur., 2021

SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management.

Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020

A low-power low-offset charge-sharing technique for double-tail comparators.

Ata Khorami, Roghayeh Saeidi, Manoj Sachdev

Microelectron. J., 2020

Energy consumption analysis of the stepwise adiabatic circuits.

Ata Khorami, Roghayeh Saeidi

Microelectron. J., 2020

SRAM Security and Vulnerability To Hardware Trojan: Design Considerations.

Roghayeh Saeidi, Morteza Nabavi, Yvon Savaria

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

Secure FPGA Design by Filling Unused Spaces.

Mansoureh Labbafniya, Roghayeh Saeidi

ISC Int. J. Inf. Secur., 2019

A low-power dynamic comparator for low-offset applications.

Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani

Integr., 2019

Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing.

Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi

Integr., 2019

An Ultra Low-power Low-offset Double-tail Comparator.

Ata Khorami, Roghayeh Saeidi, Mohammad Sharifkhani, Nima Taherinejad

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018

Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs.

Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA.

Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Behzad Zeinali, Farshad Moradi

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Novel Sensing Circuit with Large Sensing Margin for Embedded Spin-Transfer Torque MRAMs.

Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

SRAM hardware Trojan.

Roghayeh Saeidi, Hossein Gharaee Garakani

Proceedings of the 8th International Symposium on Telecommunications, 2016

Low power and roboust FinFET SRAM cell using independent gate control.

Leila Bagheriye, Roghayeh Saeidi, Siroos Toofan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2014

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell.

Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Subthreshold Symmetric SRAM Cell With High Read Stability.

Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013

A 32kb 90nm 9T-cell sub-threshold SRAM with improved read and write SNM.

Milad Zamani, Sina Hassanzadeh, Khosrow Hajsadeghi, Roghayeh Saeidi

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

A novel low power 8T-cell sub-threshold SRAM with improved read-SNM.

Sina Hassanzadeh, Milad Zamani, Khosrow Hajsadeghi, Roghayeh Saeidi

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2011

A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria.

Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2006

A 5 GHz CMOS low noise amplifier with a 3.25 turn spiral inductor for IEEE802.16a.

Fatemeh Kalantari, Nasser Masoumi, Nafiseh Gholampour, Roghayeh Saeidi

Proceedings of the IEEE Wireless Communications and Networking Conference, 2006

2005

Noise reduction of consecutive images using a new adaptive weighted averaging filter.

Mahmoud Saeidi, Seyed Ahmad Motamedi, Alireza Behrad, Behzad Saeidi, Roghayeh Saeidi, Reza Saeidi

Proceedings of the Signal and Image Processing (SIP 2005), 2005