Roger Loo

According to our database, Roger Loo authored at least 8 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts.

Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning.

Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo, P. Wong, A. Sepulveda Marquez, B. T. Chan, Jérôme Mitard, S. Subramanian, S. Demuynck, E. Dentoni Litta, N. Horiguchi, S. Samavedam, S. Biesemans

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Comprehensive 300 mm process for Silicon spin qubits with modular integration.

A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, Ruoyu Li, Iuliana P. Radu, Pol Van Dorpe, Kristiaan De Greve

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

NPN Si/SiGe memory selector with non-linearity>10⁵ and ON-current>6MA/cm².

Gaspard Hiblot, Taras Ravsher, Roger Loo, Bhuvaneshwari Yengula Venkata Ramana, Nathali Franchina-Vergel, Andrea Fantini, Shamin Houshmand Sharifi, Nina Bazzazian, Kurt Wostyn, Loris Angelo Labbate, Sebastien Couet, Gouri Sankar Kar

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Yusuke Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections.

A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo, Hiroaki Arimura, R. Rodriguez, F. Sebaai, S. Iacovo, Kevin Vandersmissen, W. Li, G. Mannaert, D. Radisic, E. Rosseel, Andriy Hikavyy, Anne Jourdain, O. Mourey, G. Gaudin, Shay Reboh, L. Le Van-Jodin, Guillaume Besnard, C. Roda Neve, Bich-Yen Nguyen, Iuliana P. Radu, E. Dentoni Litta, N. Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

60Gb/s waveguide-coupled O-band GeSi quantum-confined Stark effect electro-absorption modulator.

Srinivasan Ashwyn Srinivasan, Clement Porret, Sadhishkumar Balakrishnan, Yoojin Ban, Roger Loo, Peter Verheyen, Joris Van Campenhout, Marianna Pantouvaki

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2018

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si_0.55Ge_0.45 implant free quantum well pFET.

Shimpei Yamaguchi, Liesbeth Witters, Jérôme Mitard, Geert Eneman, Geert Hellings, Andriy Hikavyy, Roger Loo, Naoto Horiguchi

Microelectron. Reliab., 2018