Roger Endrigo Carvalho Porto

According to our database1, Roger Endrigo Carvalho Porto authored at least 14 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing.
J. Real Time Image Process., 2021

2020
UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders.
J. Real Time Image Process., 2020

2PSA: An Optimized and Flexible Power-Precision Scalable Adder.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2019
Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2017
Energy-efficient motion estimation with approximate arithmetic.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

2010
Homogeneity and distortion-based intra mode decision architecture for H.264/AVC.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2007
Design and FPGA Prototyping of a H.264/AVC Main Profile.
J. Braz. Comput. Soc., 2007

FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

High Throughput Architecture for Forward Transforms Module of H.264/AVC Video Coding Standard.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High throughput architecture for H.264/AVC forward transforms block.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004
Project Space Exploration on the 2-D DCT Architecture of a JPEG Compressor Directed to FPGA Implementation.
Proceedings of the 2004 Design, 2004


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