Roger C. Goerl

According to our database1, Roger C. Goerl authored at least 7 papers between 2017 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
PCoSA: A product error correction code for use in memory devices targeting space applications.
Integr., 2020

Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Error Coverage, Reliability and Cost Analysis of Fault Tolerance Techniques for 32-bit Memories used on Space Missions.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019
Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy.
J. Electron. Test., 2019

A New Approach to Guarantee Critical Task Schedulability in TDMA-Based Bus Access of Multicore Architecture.
Proceedings of the IEEE Latin American Test Symposium, 2019

2018
An efficient EDAC approach for handling multiple bit upsets in memory array.
Microelectron. Reliab., 2018

2017


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