Roel Uytterhoeven
Orcid: 0000-0001-8705-6784
According to our database1,
Roel Uytterhoeven
authored at least 7 papers
between 2017 and 2024.
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Bibliography
2024
11.3 Metis AIPU: A 12nm 15TOPS/W 209.6TOPS SoC for Cost- and Energy-Efficient Inference at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor.
IEEE J. Solid State Circuits, 2022
Energy and side-channel security evaluation of near-threshold cryptographic circuits in 28nm FD-SOI technology.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022
2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
DVAFS: Trading computational accuracy for energy through dynamic-voltage-accuracy-frequency-scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017