Rodrigo Travessini

According to our database, Rodrigo Travessini authored at least 4 papers between 2018 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy.

Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Roger C. Goerl, Fabian Luis Vargas, Eduardo Augusto Bezerra

J. Electron. Test., 2019

2018

A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs.

Victor M. Goncalves Martins, Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Marcelo Daniel Berejuck, Eduardo Augusto Bezerra

Microelectron. Reliab., 2018

Processor checkpoint recovery for transient faults in critical applications.

Paulo Ricardo Cechelero Villa, Rodrigo Travessini, Fabian Luis Vargas, Eduardo Augusto Bezerra

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Processor core profiling for SEU effect analysis.

Rodrigo Travessini, Paulo Ricardo Cechelero Villa, Fabian Luis Vargas, Eduardo Augusto Bezerra

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018