Rochit Rajsuman

According to our database, Rochit Rajsuman authored at least 39 papers between 1987 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2006

Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test.

Sunil R. Das, Rochit Rajsuman

IEEE Trans. Instrum. Meas., 2006

Towards The Methodology of On-line Diagnosis.

Rochit Rajsuman

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

Innovation In Test: Where Are We.

Rochit Rajsuman

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

2005

Architecture and design of an open ATE to incubate the development of third-party instruments.

Rochit Rajsuman, Masuda Noriyuki, Kazuhiro Yamashita

IEEE Trans. Instrum. Meas., 2005

Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test.

Sunil R. Das, Rochit Rajsuman

IEEE Trans. Instrum. Meas., 2005

2004

Open Architecture Test System: System Architecture and Design.

Rochit Rajsuman, Masuda Noriyuki

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Overview of the Open Architecture Test System.

Rochit Rajsuman

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

New opportunities with the open architecture test system.

Rochit Rajsuman

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Opportunities with the open architecture test system.

Kazumi Hatayama, Rochit Rajsuman

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Architecture, design, and application of an event-based test system.

Rochit Rajsuman

IEEE Trans. Instrum. Meas., 2003

Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)].

Sunil R. Das, Rochit Rajsuman

IEEE Trans. Instrum. Meas., 2003

2002

Can IC Test Learn from How a Tester is Tested.

Rochit Rajsuman

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Testing The Tester.

Rochit Rajsuman

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Extending EDA Environment From Design to Test.

Rochit Rajsuman

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Guest Editors' Intoduction: The New World of Large Embedded Memories.

Rochit Rajsuman, Francky Catthoor

IEEE Des. Test Comput., 2001

Design and Test of Large Embedded Memories: An Overview.

Rochit Rajsuman

IEEE Des. Test Comput., 2001

Test and repair of large embedded DRAMs. I.

Roderick McConnell, Rochit Rajsuman, Eric A. Nelson, Jeffrey H. Dreibelbis

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000

Iddq testing for CMOS VLSI.

Rochit Rajsuman

Proc. IEEE, 2000

A new paradigm in test for the next millennium.

Jerry Katz, Rochit Rajsuman

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999

Testing a system-on-a-chip with embedded microprocessor.

Rochit Rajsuman

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1997

VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing.

Suntae Hwang, Rochit Rajsuman

VLSI Design, 1997

1996

Challenge of the 90's: Testing CoreWare^TM Based ASICs.

Rochit Rajsuman

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Testable design of BiCMOS circuits for stuck-open fault detection using single patterns.

Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Rochit Rajsuman

IEEE J. Solid State Circuits, August, 1995

1994

STD Architecture: A Practical Approach to Test M-Bits Random Access Memories.

Rochit Rajsuman, Kamal Rajkanan

VLSI Design, 1994

Special Issue on Digital Hardware Testing.

Rochit Rajsuman

VLSI Design, 1994

A new testing method for EEPLA.

Rochit Rajsuman

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

<i>I_DDQ</i> Detection of CMOS Bridging Faults by Stuck-At Fault Tests.

Suntae Hwang, Rochit Rajsuman, Scott Davidson

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

Coverage of Bridging Faults by Random Testing in I_DDQ Test Environment.

Rochit Rajsuman, David A. Penry

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

An Architecture To Test Random Access Memories.

Rochit Rajsuman

Proceedings of the Fifth International Conference on VLSI Design, 1992

An analysis and simulation of multiple ring token networks.

David A. Vasko, Rochit Rajsuman

Proceedings of the 17th Conference on Local Computer Networks, 1992

1991

An analysis and testing of operation induced faults in MOS VLSI.

Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya, Juney Park

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

An analysis of feedback bridging faults in MOS VLSI.

Rochit Rajsuman

Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

1990

Implementation of switch network logic in SOI.

Rochit Rajsuman

IEEE J. Solid State Circuits, June, 1990

On the testing of microprogrammed processor.

Suntae Hwang, Rochit Rajsuman, Yashwant K. Malaiya

Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990

1989

CMOS open-fault detection in the presence of glitches and timing skews.

Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya

IEEE J. Solid State Circuits, August, 1989

CMOS stuck-open fault testability.

Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana

IEEE J. Solid State Circuits, February, 1989

Limitations of switch level analysis for bridging faults.

Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

CMOS Stuck-open Fault Detection Using Single Test Patterns.

Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1987

On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates.

Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987