Robin Lee
Orcid: 0000-0001-7209-3929
According to our database1,
Robin Lee
authored at least 12 papers
between 2009 and 2023.
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Bibliography
2023
A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2021
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V<sub>MIN</sub> Applications.
IEEE J. Solid State Circuits, 2021
2020
15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2018
Evaluation of Parallel Tempering to Accelerate Bayesian Parameter Estimation in Systems Biology.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
2017
12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2014
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC<sup>2</sup>RA) circuitry achieving 3x reduction on speed variation for single ended arrays.
Proceedings of the Symposium on VLSI Circuits, 2012
2010
A Differential Data-Aware Power-Supplied (D <sup>2</sup> AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications.
IEEE J. Solid State Circuits, 2010
2009
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs.
IEEE J. Solid State Circuits, 2009
Int. J. Decis. Support Syst. Technol., 2009