Roberto Zafalon
According to our database1,
Roberto Zafalon
authored at least 32 papers
between 1998 and 2013.
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Bibliography
2013
Proceedings of the 2013 IEEE 14th International Conference on Mobile Data Management, Milan, Italy, June 3-6, 2013, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011
2010
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2006
Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.
J. Low Power Electron., 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach.
Integr., 2005
Des. Autom. Embed. Syst., 2005
Proceedings of the Integrated Circuit and System Design, 2005
Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor.
Proceedings of the Seventh International Workshop on Computer Architectures for Machine Perception (CAMP 2005), 2005
2004
Proceedings of the Integrated Circuit and System Design, 2004
Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the Ultra Low-Power Electronics and Design, 2004
2003
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the 2003 Design, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems.
Des. Autom. Embed. Syst., 2002
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002
Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques.
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
1999
Proceedings of the 36th Conference on Design Automation, 1999
Fast and accurate power verification of a Viterbi decoder IP based on mixed-level power simulation technique with automatic spatio-temporal circuit partitioning.
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998