Roberto Sierra
Orcid: 0000-0002-8657-1781
According to our database1,
Roberto Sierra
authored at least 7 papers
between 2009 and 2019.
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Bibliography
2019
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs.
Integr., 2019
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2018
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
2015
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2014
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes.
J. Syst. Archit., 2014
2012
Turning control flow graphs into function calls: Code generation for heterogeneous architectures.
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
2009