Roberto R. Osorio

According to our database, Roberto R. Osorio authored at least 33 papers between 1995 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL.

Manuel de Castro, Francisco J. Andújar, Roberto R. Osorio, Rocío Carratalá-Sáez, Diego R. Llanos

CoRR, 2024

Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools.

Manuel de Castro, Roberto R. Osorio, Francisco J. Andujar, Rocío Carratalá-Sáez, Yuri Torres, Diego R. Llanos

CoRR, 2024

2023

Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL.

Manuel de Castro, Roberto R. Osorio, David López Vilariño, Arturo González-Escribano, Diego R. Llanos

J. Supercomput., June, 2023

Floating Point Calculation of the Cube Function on FPGAs.

Roberto R. Osorio

IEEE Trans. Parallel Distributed Syst., 2023

2022

An efficient ant colony optimization framework for HPC environments.

Patricia González, Roberto R. Osorio, Xoán C. Pardo, Julio R. Banga, Ramón Doallo

Appl. Soft Comput., 2022

2019

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors.

Roberto R. Osorio, Gabriel Rodríguez

IEEE Access, 2019

A Microprogrammed Approach for Implementing Statecharts.

Javier Cereijo García, Roberto R. Osorio

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities.

Javier Cereijo García, Roberto R. Osorio

Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2016

A fast algorithm for constructing nearly optimal prefix codes.

Roberto R. Osorio, Patricia González

Softw. Pract. Exp., 2016

Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model.

Roberto R. Osorio

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2013

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard.

Roberto R. Osorio, Javier D. Bruguera

J. Signal Process. Syst., 2013

Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes.

Iván Cores, Gabriel Rodríguez, María J. Martín, Patricia González, Roberto R. Osorio

New Gener. Comput., 2013

Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks.

Angela Souto Vieites, Roberto R. Osorio

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Fast Construction of Nearly-Optimal Prefix Codes without Probability Sorting.

Roberto R. Osorio, Patricia González

Proceedings of the 2012 Data Compression Conference, Snowbird, UT, USA, April 10-12, 2012, 2012

2011

Performance analysis of massively parallel embedded hardware architectures for retinal image processing.

Alejandro Nieto, Víctor M. Brea, David López Vilariño, Roberto R. Osorio

EURASIP J. Image Video Process., 2011

2009

A digital cellular-based system for retinal vessel-tree extraction.

Cesar Diaz-Resco, Alejandro Nieto, Roberto R. Osorio, Víctor M. Brea, David López Vilariño

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

High Performance Image Processing on a Massively Parallel Processor Array.

Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bruguera

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

An FPGA architecture for CABAC decoding in manycore systems.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

Entropy Coding on a Programmable Processor Array for Multimedia SoC.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

High-Throughput Architecture for H.264/AVC CABAC Compression System.

Roberto R. Osorio, Javier D. Bruguera

IEEE Trans. Circuits Syst. Video Technol., 2006

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization.

Javier D. Bruguera, Roberto R. Osorio

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture coding.

Gauthier Lafruit, Eric Delfosse, Roberto R. Osorio, Wolfgang van Raemdonck, Vissarion Ferentinos

IEEE Trans. Circuits Syst. Video Technol., 2004

Arithmetic Coding Architecture for H.264/AVC CABAC Compression System.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003

High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression.

Roberto R. Osorio, Bart Vanhoof

J. VLSI Signal Process., 2003

2002

Bitstream Syntax Description Language for 3D MPEG-4 view-dependent texture streaming.

Roberto R. Osorio, Sylvain Devillers, Eric Delfosse, Myriam Amielh, Gauthier Lafruit

Proceedings of the 2002 International Conference on Image Processing, 2002

2000

Architectures for arithmetic coding in image compression.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the 10th European Signal Processing Conference, 2000

1999

New model for arithmetic coding/decoding of multilevel images based on a cache memory.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory.

Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera

Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997

A VLSI implementation of an arithmetic coder for image compression.

Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera

Proceedings of the 23rd EUROMICRO Conference '97, 1997

New arithmetic coder/decoder architectures based on pipelining.

Roberto R. Osorio, Javier D. Bruguera

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

1995

Digit On-line Large Radix CORDIC Rotator.

Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995