Roberto Nonis
According to our database1,
Roberto Nonis
authored at least 33 papers
between 2005 and 2023.
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Bibliography
2023
A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., May, 2023
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
2021
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.
IEEE J. Solid State Circuits, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall.
Proceedings of the 1st IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2015
Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters.
Proceedings of the ESSCIRC Conference 2015, 2015
2013
IEEE J. Solid State Circuits, 2013
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2010
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl., 2010
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
2007
Modeling and design of low power integrated circuits for frequency synthesis in CMOS technology.
PhD thesis, 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
2005
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture.
IEEE J. Solid State Circuits, 2005