Roberto Muscedere
According to our database1,
Roberto Muscedere
authored at least 39 papers
between 1999 and 2020.
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Bibliography
2020
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model.
IEEE Trans. Circuits Syst., 2020
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2020
2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
2018
Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Reliability of Physical Unclonable Function under Temperature and Supply Voltage Variations.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A Fully Serial-In Parallel-Out Digit-Level Finite Field Multiplier in 𝔽<sub>2<sup>m</sup></sub> Using Redundant Representation.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
Improved particle filter based on WLAN RSSI fingerprinting and smart sensors for indoor localization.
Comput. Commun., 2016
2015
Low power design of a word-level finite field multiplier using Reordered Normal Basis.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A GPU implementation of the Montgomery multiplication algorithm for elliptic curve cryptography.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Int. J. High Perform. Syst. Archit., 2011
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011
Image processing technique for segmenting microstructural porosity of laser-welded thermoplastics.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basis.
IET Circuits Devices Syst., 2010
High-speed and low-power reconfigurable architectures of 2-digit two-dimensional logarithmic number system-based recursive multipliers.
IET Circuits Devices Syst., 2010
2009
IEEE Trans. Instrum. Meas., 2009
Flexible real-time cost-effective high-throughput inspection system for pharmaceutical capsules.
J. Electronic Imaging, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
High speed VLSI implementation of a finite field multiplier using redundant representation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
EURASIP J. Adv. Signal Process., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
A Hardware Efficient Very Large Bit Word Binary to Double Base Number System Converter for Encryption Applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2005
Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables.
IEEE Trans. Computers, 2005
A Low-Power Two-Digit Multi-dimensional Logarithmic Number System Filterbank Architecture for a Digital Hearing Aid.
EURASIP J. Adv. Signal Process., 2005
2002
On the use of hash functions for defect detection in textures for in-camera web inspection systems.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems Using Arrays of Range Addressable Look-Up Tables.
Proceedings of the 13th IEEE International Conference on Application-Specific Systems, 2002
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
An In-Camera Data Stream Processing System for Defect Detection in Web Inspection Tasks.
Real Time Imaging, 1999