Roberto Esper-Chaín

According to our database1, Roberto Esper-Chaín authored at least 9 papers between 1998 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2016
Hardware platform for wide-area vehicular sensor networks with mobile nodes.
Veh. Commun., 2016

2008
GMDS: Hardware implementation of novel real output queuing architecture.
Proceedings of the Design, Automation and Test in Europe, 2008

2006
A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe Technology.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Low Power 2.5 Gbps 1: 32 Deserializer in SiGe BiCMOS Technology.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

2005
A gigabit multidrop serial backplane for high-speed digital systems based on asymmetrical power splitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Experimental gigabit multidrop serial backplane for high speed digital systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Split-engine packet classification: a novel approach to multi-field packet classification on high performance routers with QoS support.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2002
Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches.
Proceedings of the Global Telecommunications Conference, 2002

1998
Hardware Mapping of a Parallel Algorithm for Matrix-Vector Multiplication Overlapping Communications and Computations.
Proceedings of the Field-Programmable Logic and Applications, 1998


  Loading...