Robert T. Golla

According to our database, Robert T. Golla authored at least 7 papers between 1994 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2013

The Next Generation 64b SPARC Core in a T4 SoC Processor.

Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister

IEEE J. Solid State Circuits, 2013

2012

Sparc T4: A Dynamically Threaded Server-on-a-Chip.

Manish K. Shah, Robert T. Golla, Greg Grohoski, Paul J. Jordan, Jama Barreh, Jeffrey Brooks, Mark Greenberg, Gideon Levinsky, Mark Luttrell, Christopher Olson, Zeid Samoail, Matt Smittle, Thomas A. Ziaja

IEEE Micro, 2012

The next-generation 64b SPARC core in a T4 SoC processor.

Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

T4: A highly threaded server-on-a-chip with native support for heterogeneous computing.

Robert T. Golla, Paul J. Jordan

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2009

Throughput-Oriented Multicore Processors.

James Laudon, Robert T. Golla, Greg Grohoski

Proceedings of the Multicore Processors and Systems, 2009

1994

POWER2 instruction cache unit.

Jama Barreh, Robert T. Golla, L. Baba Arimilli, Paul J. Jordan

IBM J. Res. Dev., 1994