Robert Najvirt

Orcid: 0000-0003-2987-5137

According to our database¹, Robert Najvirt authored at least 22 papers between 2012 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2023

The Hidden Behavior of a D-Latch.

[BibT_eX]

[DOI]

Jürgen Maier

Andreas Steininger

Robert Najvirt

IEEE Trans. Circuits Syst. I Regul. Pap., April, 2023

ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

2022

On SAT-Based Model Checking of Speed-Independent Circuits.

[BibT_eX]

[DOI]

Florian Huemer

Robert Najvirt

Andreas Steininger

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021

An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020

A Faithful Binary Circuit Model.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018

A faithful binary circuit model with adversarial noise.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Measuring Metastability with Free-Running Clocks.

[BibT_eX]

[DOI]

Robert Najvirt

Thomas Polzer

Andreas Steininger

Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016

On the Appropriate Handling of Metastable Voltages in FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior?

[BibT_eX]

[DOI]

Andreas Steininger

Robert Najvirt

Jürgen Maier

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

The Metastable Behavior of a Schmitt-Trigger.

[BibT_eX]

[DOI]

Andreas Steininger

Jürgen Maier

Robert Najvirt

Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015

A versatile and reliable glitch filter for clocks.

[BibT_eX]

[DOI]

Robert Najvirt

Andreas Steininger

Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Experimental Validation of a Faithful Binary Circuit Model.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

A pausible clock with crystal oscillator accuracy.

[BibT_eX]

[DOI]

Robert Najvirt

Andreas Steininger

Proceedings of the European Conference on Circuit Theory and Design, 2015

Containment of Metastable Voltages in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Towards binary circuit models that faithfully capture physical solvability.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

How to Synchronize a Pausible Clock to a Reference.

[BibT_eX]

[DOI]

Robert Najvirt

Andreas Steininger

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014

Faithful Glitch Propagation in Binary Circuit Models.

[BibT_eX]

[DOI]

CoRR, 2014

Equivalence of clock gating and synchronization with applicability to GALS communication.

[BibT_eX]

[DOI]

Robert Najvirt

Andreas Steininger

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

2013

A Multi-Credit Flow Control scheme for asynchronous NoCs.

[BibT_eX]

[DOI]

Syed Rameez Naqvi

Robert Najvirt

Andreas Steininger

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs.

[BibT_eX]

[DOI]

Robert Najvirt

Syed Rameez Naqvi

Andreas Steininger

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012

A Generic Architecture for Robust Asynchronous Communication Links.

[BibT_eX]

[DOI]

Jakob Lechner

Robert Najvirt

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Robert Najvirt

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