Robert Michael Owens

Proceedings of the 35th Conference on Design Automation, 1998

1997

A fast algorithm for minimizing the Elmore delay to identified critical sinks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Motion Analysis on the Micro Grained Array Processor.

[BibT_eX]

[DOI]

Heung-Nam Kim

Real Time Imaging, 1997

Power-Area Trade-Offs in Divided Word Line Memory Arrays.

[BibT_eX]

[DOI]

Meng-Fan Chang

J. Circuits Syst. Comput., 1997

A Simulation Methodology for Software Energy Evaluation.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Techniques for low energy software.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Analysis of power consumption in memory hierarchies.

[BibT_eX]

[DOI]

Patrick Hicks

Matthew Walnock

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Mixed-autonomy local interconnect for reconfigurable SIMD arrays.

[BibT_eX]

[DOI]

Proceedings of the Fourth International on High-Performance Computing, 1997

A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

The MGAP Family of Processor Arrays.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

1996

Architectures for wavelet transforms: A survey.

[BibT_eX]

[DOI]

Chaitali Chakrabarti

J. VLSI Signal Process., 1996

An optimal time multiplication free algorithm for edge detection on a mesh.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1996

Transistor sizing for low power CMOS circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Design tradeoffs in high speed multipliers and FIR filters.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Power comparisons for barrel shifters.

[BibT_eX]

[DOI]

Kevin P. Acken

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Instruction level power profiling.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Simultaneous speech segmentation and phoneme recognition using dynamic programming.

[BibT_eX]

[DOI]

Thomas P. Kelliher

Proceedings of the 1996 IEEE International Conference on Acoustics, 1996

Some Issues in Gray Code Addressing.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Recent Developments in Performance Driven Steiner Routing: An Overview.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Energy Characterization based on Clustering.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

A Common Architecture For The DWT and IDWT.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

An Architectural Design For Parallel Fractal Compression.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

1995

Digit pipelined arithmetic on fine-grain array processors.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1995

Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A simulation methodology for evaluating parallel computers.

[BibT_eX]

[DOI]

Paul Keltcher

Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Unifying carry-sum and signed-digital number representations for low power.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

High-throughput and low-power DSP using clocked-CMOS circuitry.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

The MGAP-2: an advanced, massively parallel VLSI signal processor.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Conference on Acoustics, 1995

A survey of architectures for the discrete and continuous wavelet transforms.

[BibT_eX]

[DOI]

Chaitali Chakrabarti

Proceedings of the 1995 International Conference on Acoustics, 1995

Fast algorithm for performance-oriented Steiner routing.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Accurate Estimation of Combinational Circuit Activity.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

Motion Estimation Algorithms on Fine Grain Array Processor.

[BibT_eX]

[DOI]

Heung-Nam Kim

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

The MGAP's programming environment and the *C++ language.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

Reducing the number of counters needed for integer multiplication.

[BibT_eX]

[DOI]

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1994

Power-delay characteristics of CMOS adders.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1994

Logic synthesis for field-programmable gate arrays.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An edge-based heuristic for Steiner routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Polynomial Time Testability of Circuits Generated by Input Decomposition.

[BibT_eX]

[DOI]

Gueesang Lee

IEEE Trans. Computers, 1994

Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1994

Dynamic Space Warping Algorithms on Fine-Graln Array Processors.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Parallel Processing, 1994

Digit pipelined discrete wavelet transform.

[BibT_eX]

[DOI]

Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994

The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS.

[BibT_eX]

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

FPGA-based synthesis of FSMs through decomposition.

[BibT_eX]

[DOI]

Wen-Lin Yang

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993

The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1993

A Massively Parallel, Micro-Grained VLSI Architecture.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on VLSI Design, 1993

Image Processing with the MGAP: A Cost Effective Solution.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Parallel Processing Symposium, 1993

A new blocked IIR algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1993

Edge detection using fine-grained parallelism in VLSI.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1993

Multi-way FSM decomposition based on interconnect complexity.

[BibT_eX]

[DOI]

Wen-Lin Yang

Proceedings of the European Design Automation Conference 1993, 1993

Digit systolic algorithms for fine-grain architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992

Efficiently computing communication complexity for multilevel logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

ELM-A Fast Addition Algorithm Discovered by a Program.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1992

ECube: An Efficient Architecture for Analyzing Time-Varying Spectra.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on VLSI Design, 1992

An AT<sup>2</sup> lower bound for wavelet transforms in VLSI.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

A micro-grained VLSI signal processor.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

PERFLEX: a performance driven module generator.

[BibT_eX]

[DOI]

Soohong Kim

Proceedings of the conference on European design automation, 1992

Experiments with a Performance Driven Module Generator.

[BibT_eX]

[DOI]

Soohong Kim

Proceedings of the 29th Design Automation Conference, 1992

Discrete wavelet transforms in VLSI.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1992

Implementing a family of high performance, micrograined architectures.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1992

1991

A Two-Dimensional, Distributed Logic Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1991

Digit Serial Multipliers.

[BibT_eX]

[DOI]

Poras T. Balsara

J. Parallel Distributed Comput., 1991

The arithmetic cube II: a second generation VLSI DSP processor.

[BibT_eX]

[DOI]

Proceedings of the 1991 International Conference on Acoustics, 1991

The Arithmetic Cube: error analysis and simulation.

[BibT_eX]

[DOI]

Proceedings of the Application Specific Array Processors, 1991

1990

A case for digit serial VLSI signal processors.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1990

Exploiting communication complexity for multilevel logic synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Being Stingy with Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1990

An integrated, multi-level synthesis system.

[BibT_eX]

[DOI]

Proceedings of the First International Workshop on Rapid System Prototyping, 1990

Test generation in circuits constructed by input decomposition.

[BibT_eX]

[DOI]

Gueesang Lee

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Logic synthesis for programmable logic devices.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Distortion processing in image matching problems.

[BibT_eX]

[DOI]

Chen-Mi Wu

Proceedings of the 1990 International Conference on Acoustics, 1990

A two-dimensional, distributed logic processor for machine vision.

[BibT_eX]

[DOI]

Proceedings of the 1990 International Conference on Acoustics, 1990

Mapping high-dimension wavefront computations to silicon.

[BibT_eX]

[DOI]

Chen-Mie Wu

Proceedings of the Application Specific Array Processors, 1990

1989

Implementing algorithms for convolution on arrays of adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1989

A Comparison of Four Two-dimensional Gate Matrix Layout Tools.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Multi-Level Logic Synthesis Using Communication Complexity.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

A comparison of two digit serial VLSI adders.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Multidimensional algorithms for VLSI processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1988

DECOMPOSER: A Synthesizer for Systolic Systems.

[BibT_eX]

[DOI]

Pao-Po Hou

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Digit pipelined processors.

[BibT_eX]

[DOI]

J. Supercomput., 1987

The Arithmetic Cube.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1987

Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial.

[BibT_eX]

[DOI]

Computer, 1987

An Overview of the Penn State Design System.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation.

[BibT_eX]

[DOI]

Jared A. Beekman

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Systolic & semi-systolic digit serial multipliers.

[BibT_eX]

[DOI]

Poras T. Balsara

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1986

A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transform.

[BibT_eX]

[DOI]

IEEE Trans. Acoust. Speech Signal Process., 1986

A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Optimal Algorithms for Mesh-Connected Parallel Processors with Serial Memories.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1986

1985

Parallel Sorting with Serial Momories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1985

1984

VLSI Sorting with Reduced Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1984

1983

Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1983

Fully Digit On-Line Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1983

An architecture for a VLSI FFT processor.

[BibT_eX]

[DOI]

Integr., 1983

Numerical limitations on the design of digit online networks.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1981

Compound algorithms for digit online arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

1979

On-Line Algorithms for the Design of Pipeline Architectures.

[BibT_eX]

[DOI]