Robert L. Franch

According to our database, Robert L. Franch authored at least 11 papers between 1988 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning.

Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2014

POWER8 design methodology innovations for improving productivity and reducing power.

Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012

A shorted global clock design for multi-GHz 3D stacked chips.

Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier

Proceedings of the Symposium on VLSI Circuits, 2012

2008

On-chip Timing Uncertainty Measurements on IBM Microprocessors.

Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem

Proceedings of the 2008 IEEE International Test Conference, 2008

2003

The physical design of on-chip interconnections.

Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Estimating the efficiency of collaborative problem-solving, with applications to chip design.

Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Giovanni Fiorenza, I. Cevdet Noyan

IBM J. Res. Dev., 2003

1997

A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file.

Robert L. Franch, J. Ji, C. L. Chen

IEEE J. Solid State Circuits, 1997

1992

Advances in Membrane Probe Technology.

January Kister, Robert L. Franch

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1989

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.

Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano

IEEE J. Solid State Circuits, October, 1989

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces.

Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.-C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle

IEEE J. Solid State Circuits, August, 1989

1988

Fast CMOS ECL receivers with 100-mV worst-case sensitivity.

Barbara A. Chappell, Terry I. Chappell, Stanley E. Schuster, Hermann M. Segmuller, James W. Allan, Robert L. Franch, Phillip J. Restle

IEEE J. Solid State Circuits, February, 1988