Robert K. Brayton

Proceedings of the 31st Conference on Design Automation, 1994

Heuristic Minimization of BDDs Using Don't Cares.

[BibT_eX]

[DOI]

Thomas R. Shiple

Ramin Hojati

Proceedings of the 31st Conference on Design Automation, 1994

Performance Optimization Using Exact Sensitization.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

Optimum Functional Decomposition Using Encoding.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

Exact Minimum Cycle Times for Finite State Machines.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

A Fully Implicit Algorithm for Exact State Minimization.

[BibT_eX]

[DOI]

Timothy Kam

Tiziano Villa

Proceedings of the 31st Conference on Design Automation, 1994

BDD Variable Ordering for Interacting Finite State Machines.

[BibT_eX]

[DOI]

Adnan Aziz

Serdar Tasiran

Proceedings of the 31st Conference on Design Automation, 1994

HSIS: A BDD-Based Environment for Formal Verification.

[BibT_eX]

[DOI]

Proceedings of the 31st Conference on Design Automation, 1994

Criteria for the Simple Path Property in Timed Automata.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Improving Language Containment Using Fairness Graphs.

[BibT_eX]

[DOI]

Ramin Hojati

Robert B. Mueller-Thuns

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Timed Boolean functions - a unified formalism for exact timing analysis.

[BibT_eX]

The Kluwer international series in engineering and computer science 270, Kluwer, ISBN: 978-0-7923-9454-9, 1994

1993

ESPRESSO-SIGNATURE: a new exact minimizer for logic functions.

[BibT_eX]

[DOI]

Jagesh V. Sanghavi

IEEE Trans. Very Large Scale Integr. Syst., 1993

Heuristic minimization of multiple-valued relations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Computing the initial states of retimed circuits.

[BibT_eX]

[DOI]

Hervé J. Touati

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Two-Level Minimization of Multivalued Functions with Large Offsets.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

Minimization of Logic Functions Using Essential Signature Sets.

[BibT_eX]

[DOI]

Jagesh V. Sanghavi

Proceedings of the Sixth International Conference on VLSI Design, 1993

Logic Optimization with Multi-Output Gates.

[BibT_eX]

[DOI]

Lisa M. Guerra

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Physically Realizable Gate Models.

[BibT_eX]

[DOI]

Paul R. Stephan

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Heuristic Minimization of Synchronous Relations.

[BibT_eX]

[DOI]

Vigyan Singhal

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Some Results on the Complexity of Boolean Functions for Table Look Up Architectures.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

The maximum set of permissible behaviors for FSM networks.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Input don't care sequences in FSM networks.

[BibT_eX]

[DOI]

Huey-Yih Wang

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Minimum padding to satisfy short path constraints.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Cube-packing and two-level minimization.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Dynamic variable reordering for BDD minimization.

[BibT_eX]

[DOI]

Eric Felt

Gary York

Proceedings of the European Design Automation Conference 1993, 1993

Resynthesis of Multi-Phase Pipelines.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Sequential Synthesis for Table Look Up Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Elimination of Dynamic hazards by Factoring.

[BibT_eX]

[DOI]

Cho W. Moon

Proceedings of the 30th Design Automation Conference. Dallas, 1993

On Computing the Transitive Closure of a State Transition Relation.

[BibT_eX]

[DOI]

Yusuke Matsunaga

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Delay Fault Coverage and Performance Tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

A Unified Approach to Language Containment and Fair CTL Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

Alternating RQ Timed Automata.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 5th International Conference, 1993

BDD-Based Debugging Of Design Using Language Containment and Fair CTL.

[BibT_eX]

[DOI]

Ramin Hojati

Robert P. Kurshan

Proceedings of the Computer Aided Verification, 5th International Conference, 1993

Logic Synthesis and Design Verification.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 5th International Conference, 1993

1992

Symbolic minimization of multilevel logic and the input encoding problem.

[BibT_eX]

[DOI]

Luciano Lavagno

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Sequential Circuit Design Using Synthesis and Optimization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

On Relationship Between ITE and BDD.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Delay Prediction for Technology-Independent Logic Equations.

[BibT_eX]

[DOI]

Paul T. Gutwin

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Graph algorithms for clock schedule optimization.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Valid clocking in wavepipelined circuits.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Automatic compositional minimization in CTL model checking.

[BibT_eX]

[DOI]

Massimiliano Chiodo

Thomas R. Shiple

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Boolean matching in logic synthesis.

[BibT_eX]

[DOI]

Mário J. Silva

Proceedings of the conference on European design automation, 1992

On the Temporal Equivalence of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

An Improved Synthesis Algorithm for Multiplexor-Based PGA's.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Solving the State Assignment Problem for Signal Transition Graphs.

[BibT_eX]

[DOI]

Luciano Lavagno

Cho W. Moon

Proceedings of the 29th Design Automation Conference, 1992

Automatic Reduction in CTL Compositional Model Checking.

[BibT_eX]

[DOI]

Thomas R. Shiple

Massimiliano Chiodo

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

Efficient <i>omega</i>-Regular Language Containment.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991

Retiming and resynthesis: optimizing sequential networks with combinational techniques.

[BibT_eX]

[DOI]

Ellen M. Sentovich

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Reduced offsets for minimization of binary-valued functions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Preserving Don't Care Conditions During Retiming.

[BibT_eX]

Ellen Sentovich

Proceedings of the VLSI 91, 1991

Incremental Synthesis for Engineering Changes.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Retiming of Circuits with Single Phase Transparent Latches.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Three-Level Decomposition with Application to PLDs.

[BibT_eX]

[DOI]

David Harrison

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Heuristic Minimazation of Multiple-Valued Relations.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing.

[BibT_eX]

[DOI]

Hervé J. Touati

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Extracting Local Don't Cares for Network Optimization.

[BibT_eX]

[DOI]

Hervé J. Touati

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Observability Relations and Observability Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Improved Logic Synthesis Algorithms for Table Look Up Architectures.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On Clustering for Minimum Delay/Area.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications.

[BibT_eX]

[DOI]

Cho W. Moon

Paul R. Stephan

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Performance Enhancement through the Generalized Bypass Transform.

[BibT_eX]

[DOI]

Sartaj Sahni

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Framework for Satisfying Input and Output Encoding Constraints.

[BibT_eX]

[DOI]

Tiziano Villa

Proceedings of the 28th Design Automation Conference, 1991

1990

Multilevel logic synthesis.

[BibT_eX]

[DOI]

Gary D. Hachtel

Proc. IEEE, 1990

The observability don't-care set and its approximations.

[BibT_eX]

[DOI]

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Implicit State Enumeration of Finite State Machines Using BDDs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Algorithms for Discrete Function Manipulation.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Timing Optimization with Testability Considerations.

[BibT_eX]

[DOI]

Kwang-Ting Cheng

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Performance Optimization of Pipelined Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs.

[BibT_eX]

[DOI]

Luciano Lavagno

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Logic Synthesis for Programmable Gate Arrays.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Timing Analysis in Precharge/Unate Networks.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Reduced Offsets for Two-Level Multi-Valued Logic Minimization.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Logic minimization for factored forms.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Fast two-level logic minimizers for multi-level logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Consistency and observability invariance in multi-level logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

An exact minimizer for Boolean relations.

[BibT_eX]

[DOI]

Fabio Somenzi

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

SLIP: a software environment for system level interactive partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Multi-level Logic Simplification Using Don't Cares and Filters.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

Efficient Prime Factorization of Logic Expressions.

[BibT_eX]

[DOI]

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Multi-level logic minimization using implicit don't cares.

[BibT_eX]

[DOI]

Christopher R. Morrison

Richard L. Rudell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Timing optimization of combinational logic.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Logic verification using binary decision diagrams in a logic synthesis environment.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

A modified approach to two-level logic minimization.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Don't cares and global flow analysis of Boolean networks.

[BibT_eX]

[DOI]

Ellen M. Sentovich

Fabio Somenzi

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

XPSim: a MOS VLSI simulator.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

1987

MIS: A Multiple-Level Logic Optimization System.

[BibT_eX]

[DOI]

Richard L. Rudell

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986

Correction to "Optimal State Assignment for Finite State Machines".

[BibT_eX]

[DOI]

Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1985

Optimal State Assignment for Finite State Machines.

[BibT_eX]

[DOI]

Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

1984

Logic Minimization Algorithms for VLSI Synthesis

[BibT_eX]

[DOI]

Gary D. Hachtel

Curtis T. McMullen

The Kluwer International Series in Engineering and Computer Science 2, Springer, ISBN: 978-1-4613-2821-6, 1984

1964

Stability Criteria for Large Networks.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 1964

1963

An Analysis of the Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel-Diode Circuit.

[BibT_eX]

[DOI]