Robert Hülle

According to our database, Robert Hülle authored at least 6 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA.

Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle

Proceedings of the 13th Mediterranean Conference on Embedded Computing, 2024

2023

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA.

Miroslav Skrbek, Pavel Kubalík, Martin Kohlík, Jaroslav Borecký, Robert Hülle

Proceedings of the 12th Mediterranean Conference on Embedded Computing, 2023

Reducing Output Response Aliasing Using Boolean Optimization Techniques.

Robert Hülle, Petr Fiser, Jan Schmidt

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2020

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing.

Jaroslav Borecký, Robert Hülle, Petr Fiser

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2018

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction.

Robert Hülle, Petr Fiser, Jan Schmidt

Microprocess. Microsystems, 2018

2017

SAT-Based ATPG for Zero-Aliasing Compaction.

Robert Hülle, Petr Fiser, Jan Schmidt

Proceedings of the Euromicro Conference on Digital System Design, 2017