Robert H. Dennard

Affiliations:
  • IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA


According to our database1, Robert H. Dennard authored at least 17 papers between 1964 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1980, "For advances in the state of the art of MOSFET devices and circuits.".

Timeline

1965
1970
1975
1980
1985
1990
1995
2000
2005
2010
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3
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Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2010
Practical Strategies for Power-Efficient Computing Technologies.
Proc. IEEE, 2010

2008
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches.
IEEE J. Solid State Circuits, 2008

2006
Silicon CMOS devices beyond scaling.
IBM J. Res. Dev., 2006

2005
Gated-diode amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A novel dynamic memory cell with internal voltage gain.
IEEE J. Solid State Circuits, 2005

2002
Challenges and future directions for the scaling of dynamic random-access memory (DRAM).
IBM J. Res. Dev., 2002

2001
Device scaling limits of Si MOSFETs and their application dependencies.
Proc. IEEE, 2001

2000
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro.
IEEE J. Solid State Circuits, 2000

Design and characteristics of n-channel insulated-gate field-effect transistors.
IBM J. Res. Dev., 2000

1999
Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions.
Proc. IEEE, 1999

1996
I<sub>DDQ</sub> Test: Sensitivity Analysis of Scaling.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Iddq Testing for High Performance CMOS - The Next Ten Years.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
CMOS scaling for high performance and low power-the next ten years.
Proc. IEEE, 1995

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.
IBM J. Res. Dev., 1995

Modeling and characterization of long on-chip interconnections for high-performance microprocessors.
IBM J. Res. Dev., 1995

1992
Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance.
IEEE J. Solid State Circuits, May, 1992

1964
A Vestigial-Sideband, Phase-Reversal Data Transmission System.
IBM J. Res. Dev., 1964


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