Robert de Simone

Alexander Schulz-Rosengarten

Damien Chabrol

Amira Methni

Proceedings of Cyber-Physical Systems and Internet of Things Week 2023, 2023

2020

Multiform Logical Time & Space for Specification of Automated Driving Assistance Systems: Work-in-Progress.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Embedded Software, 2020

Multiform Logical Time & Space for Mobile Cyber-Physical System With Automated Driving Assistance System.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia-Pacific Software Engineering Conference, 2020

2018

Beyond Time-Triggered Co-simulation of Cyber-Physical Systems for Performance and Accuracy Improvements.

[BibT_eX]

[DOI]

Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

Time in SCCharts.

[BibT_eX]

[DOI]

Reinhard von Hanxleden

Julien Deantoni

Proceedings of the 2018 Forum on Specification & Design Languages, 2018

2017

Explicit Control of Dataflow Graphs with MARTE/CCSL.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Model-Driven Engineering and Software Development, 2017

2016

Instant-Based and State-Based Analysis of Infinite Logical Clock.

[BibT_eX]

[DOI]

Proceedings of the Structured Object-Oriented Formal Language and Method, 2016

Divergence Detection for CCSL Specification via Clock Causality Chain.

[BibT_eX]

[DOI]

Qingguo Xu

Julien DeAntoni

Proceedings of the Dependable Software Engineering: Theories, Tools, and Applications, 2016

Keynote talk II: Multiform logical time for Me/Mo-codesign.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

A formal approach to the mapping of tasks on an heterogenous multicore, energy-aware architecture.

[BibT_eX]

[DOI]

Emilien Kofman

Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Using SystemC Cyber Models in an FMI Co-Simulation Environment: Results and Proposed FMI Enhancements.

[BibT_eX]

[DOI]

Stefano Centomo

Julien Deantoni

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core Architectures.

[BibT_eX]

[DOI]

Emilien Kofman

ACM Trans. Embed. Comput. Syst., 2015

Correctness issues on MARTE/CCSL constraints.

[BibT_eX]

[DOI]

Sci. Comput. Program., 2015

Efficient FFT mapping on GPU for radar processing application: modeling and implementation.

[BibT_eX]

[DOI]

Mohamed Amine Bergach

CoRR, 2015

On the Scalability of Constraint Solving for Static/Off-Line Real-Time Scheduling.

[BibT_eX]

[DOI]

Raul Gorcitz

Emilien Kofman

Thomas Carle

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2015

2014

Reconciling performance and predictability on a many-core through off-line mapping.

[BibT_eX]

[DOI]

Franck Wajsbürt

Zhen Zhang

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Execution of heterogeneous models for thermal analysis with a multi-view approach.

[BibT_eX]

[DOI]

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Static Mapping of Real-Time Applications onto Massively Parallel Processor Arrays.

[BibT_eX]

[DOI]

Thomas Carle

Manel Djemal

Zhen Zhang

Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013

Explicit routing schemes for implementation of cellular automata on processor arrays.

[BibT_eX]

[DOI]

Nat. Comput., 2013

Safe CCSL specifications and marked graphs.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Schedulability Analysis with CCSL Specifications.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia-Pacific Software Engineering Conference, 2013

2012

Periodic scheduling of marked graphs using balanced binary words.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 2012

Programmable routers for efficient mapping of applications onto NoC-based MPSoCs.

[BibT_eX]

[DOI]

Zhen Zhang

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011

Logical time: specification vs. implementation.

[BibT_eX]

[DOI]

ACM SIGSOFT Softw. Eng. Notes, 2011

From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2011

2010

Introduction to special issue: papers from UML&FM'2009.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2010

The clock constraint specification language for building timed causality models - Application to synchronous data flow graphs.

[BibT_eX]

[DOI]

Innov. Syst. Softw. Eng., 2010

Polychronous Analysis of Timing Constraints in UML MARTE.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

From Synchronous Specifications to Statically Scheduled Hard Real-Time Implementations.

[BibT_eX]

[DOI]

Proceedings of the Synthesis of Embedded Software, 2010

Formal Modeling of Embedded Systems with Explicit Schedules and Routes.

[BibT_eX]

[DOI]

Anthony Coadou

Proceedings of the Synthesis of Embedded Software, 2010

The Time Model of Logical Clocks Available in the OMG MARTE Profile.

[BibT_eX]

[DOI]

Proceedings of the Synthesis of Embedded Software, 2010

2009

Latency-Insensitive Design: Retry Relay-Station and Fusion Shell.

[BibT_eX]

[DOI]

Anthony Coadou

Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

IP-XACT components with abstract time characterization.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2009

Clock-driven distributed real-time implementation of endochronous synchronous programs.

[BibT_eX]

[DOI]

Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

Synchronous Hypothesis and Polychronous Languages.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Design and Verification, 2009

2008

MARTE: a profile for RT/E systems modeling, analysis-<i>and simulation</i>?

[BibT_eX]

[DOI]

Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008

Dealing with AADL End-to-End Flow Latency with UML MARTE.

[BibT_eX]

[DOI]

Su-Young Lee

Proceedings of the 13th International Conference on Engineering of Complex Computer Systems (ICECCS 2008), March 31 2008, 2008

Event-Triggered vs. Time-Triggered Communications with UML MARTE.

[BibT_eX]

[DOI]

Laurent Rioux

Proceedings of the Forum on specification and Design Languages, 2008

MARTE vs. AADL for Discrete-Event and Discrete-Time Domains.

[BibT_eX]

[DOI]

Proceedings of the Languages for Embedded Systems and their Applications, 2008

2007

Preface.

[BibT_eX]

[DOI]

Alain Girault

Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, 2007

Formal Methods for Scheduling of Latency-Insensitive Designs.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2007

Modeling Time(s).

[BibT_eX]

[DOI]

Proceedings of the Model Driven Engineering Languages and Systems, 2007

MARTE: Also an UML Profile for Modeling AADL Applications.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Engineering of Complex Computer Systems (ICECCS 2007), 2007

Time Modeling in MARTE.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

Modeling of immediate vs. delayed data communications: from AADL to UML Marte.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

Necessary and sufficient conditions for deterministic desynchronization.

[BibT_eX]

[DOI]

Proceedings of the 7th ACM & IEEE International conference on Embedded software, 2007

2006

Towards a "Synchronous Reactive" UML profile?

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2006

Syntax-driven optimisations for reachable state space construction of ESTEREL programs.

[BibT_eX]

[DOI]

Eric Vecchié

Int. J. Embed. Syst., 2006

Latency-insensitive design and central repetitive scheduling.

[BibT_eX]

[DOI]

Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

2005

The Synchronous Hypothesis and Synchronous Languages.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Handbook., 2005

Loops in esterel.

[BibT_eX]

[DOI]

Olivier Tardieu

ACM Trans. Embed. Comput. Syst., 2005

Guidelines for a graduate curriculum on embedded software and systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2005

Another Glance at Relay Stations in Latency-Insensitive Design.

[BibT_eX]

[DOI]

Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

P2I: An Innovative MDA Methodology for Embedded Real-Time System.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Syntax-Driven Reachable State Space Construction of Synchronous Reactive Programs.

[BibT_eX]

[DOI]

Eric Vecchié

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2004

Syntax-driven Behavior Partitioning for Model-checking of Esterel Programs.

[BibT_eX]

[DOI]

Eric Vecchié

Proceedings of the Third International Workshop on Synchronous Languages, 2004

Curing schizophrenia by program rewriting in Esterel.

[BibT_eX]

[DOI]

Olivier Tardieu

Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

2003

The synchronous languages 12 years later.

[BibT_eX]

[DOI]

Proc. IEEE, 2003

Instantaneous Termination in Pure Esterel.

[BibT_eX]

[DOI]

Olivier Tardieu

Proceedings of the Static Analysis, 10th International Symposium, 2003

Optimizations for Faster Execution of Esterel Programs.

[BibT_eX]

[DOI]

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

2002

Ninth International Conference on Concurrency Theory 1998 - Editorial.

[BibT_eX]

[DOI]

Davide Sangiorgi

Theor. Comput. Sci., 2002

2000

ESTEREL: a formal method applied to avionic software development.

[BibT_eX]

[DOI]

Sci. Comput. Program., 2000

1996

The SL Synchronous Language.

[BibT_eX]

[DOI]

Frédéric Boussinot

IEEE Trans. Software Eng., 1996

Automated design of communication protocols using ESTEREL.

[BibT_eX]

[DOI]

Christophe Diot

Christian Huitema

J. High Speed Networks, 1996

The FC2TOOLS Set (Tool Demonstration).

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1996

Verifying Synchronous Reactive Systems Programmed in ESTEREL.

[BibT_eX]

[DOI]

Proceedings of the Formal Techniques in Real-Time and Fault-Tolerant Systems, 1996

The FC2TOOLS Set.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 8th International Conference, 1996

1995

Using PO Methods for Verfying Behavioural Equivalences.

[BibT_eX]

Monica Lara de Souza

Proceedings of the Formal Description Techniques VIII, 1995

1994

Model-Based Verification Methods and Tools (Abstract).

[BibT_eX]

[DOI]

Jean-Claude Fernandez

Joseph Sifakis

Proceedings of the CONCUR '94, 1994

Compositional Semantics of ESTEREL and Verification by Compositional Reductions.

[BibT_eX]

[DOI]

Annie Ressouche

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1992

Auto/Autograph.

[BibT_eX]

[DOI]

Valérie Roy

Formal Methods Syst. Des., 1992

Symbolic Bisimulation Minimisation.

[BibT_eX]

[DOI]

Amar Bouali

Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992

1991

The ESTEREL language.

[BibT_eX]

[DOI]

Frédéric Boussinot

Proc. IEEE, 1991

Causal Models for Rational Algebraic Processes.

[BibT_eX]

[DOI]

Amar Bouali

Proceedings of the CONCUR '91, 1991

1989

Process Calculi, from Theory to Practice: Verification Tools.

[BibT_eX]

[DOI]

Proceedings of the Automatic Verification Methods for Finite State Systems, 1989

1985

Higher-Level Synchronising Devices in Meije-SCCS.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 1985

Petri Nets and Algebraic Calculi of Processes.

[BibT_eX]

[DOI]

Gérard Boudol

Gérard Roucairol

Proceedings of the STACS 85, 1985

1984

Langages Infinitaires et Produit de Mixage.

[BibT_eX]

[DOI]

Theor. Comput. Sci., 1984

On Meije and SCCS: Infinite Sum Operators VS. Non-Guarded Definitions.

[BibT_eX]

[DOI]